STT-MRAM Cell Array Segmentation for Back-Hopping Prevention
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Solution Overview
Problem
In spin transfer torque magnetic random access memory (STT-MRAM) devices, the varying switching currents required for different memory cells due to distribution characteristics lead to operation failures and inability to write data effectively, as excessive currents can cause Joule heating and back hopping, resulting in improper magnetization direction alignment and resistance changes.
Innovation Solution
A method and device that apply sequentially decreasing switching pulses with varying current levels and pulse widths to ensure proper data writing across memory cells, with the final pulse having a current level equal to or lower than the minimum required, preventing back hopping and ensuring accurate data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single high switching current is applied to all memory cells, then memory cells requiring higher current can be switched, but memory cells requiring lower current experience Joule heating and back hopping causing operation failure
Solution Approach 1:
The patent segments the memory cell array into multiple groups (first group, second group, etc.) and applies different switching current levels to each group. Specifically, a first switching current is applied to a first group of memory cells, and a second switching current lower than the first is applied to a second group of memory cells. This segmentation allows each group to receive the appropriate current level for reliable operation without experiencing harmful Joule heating or back hopping effects.
Solution Approach 2:
The patent implements local quality by tailoring the switching current characteristics to the specific requirements of different memory cell groups. Each group of memory cells is assigned a switching current level matched to its electrical characteristics. This localized optimization ensures that each memory cell receives the precise current needed for reliable magnetization switching without excessive current causing harmful thermal effects.
2Manufacturing precision
If switching currents are optimized for each individual memory cell, then exact data writing can be achieved, but device complexity increases due to need for multiple current levels
Solution Approach 1:
The patent divides the memory cell array into discrete groups and assigns specific switching current levels to each group. This segmentation approach achieves precise data writing for each group while maintaining manageable device complexity by organizing memory cells into a finite number of current-level groups rather than requiring individual customization for each cell.
Solution Approach 2:
The patent utilizes parameter changes by varying the switching current level parameter across different memory cell groups. By changing the current level parameter from a first switching current for the first group to a second switching current for the second group, the system achieves precise control adapted to different electrical characteristics while maintaining a systematic approach that doesn't overly complicate the device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for exact data writing in memory cells with diverse electrical characteristics, preventing back hopping and ensuring reliable data storage by aligning spin polarities correctly across all cells, even those requiring lower switching currents.
Implementation Method 1
spin transfer torque magnetic random access memory (STT-MRAM) device
Implementation Method 2
excessive currents can cause Joule heating and back hopping
Data Source
AI summary
In a method of writing data in an MRAM device, a first operation unit is selected in a plurality of memory cells of the MRAM device. First to n-th switching pulses are sequentially applied to the first operation unit to write data in first to n-th groups of memory cells of the first operation unit, respectively. The n-th switching pulse may have a current level lower than that of an (n−1)th switching pulse, where n is an integer larger than at least 1. The n-th switching pulse may have a pulse width narrower than that of an (n−1)th switching pulse, where n is an integer larger than at least 1. The technique can be repeated for a second operation unit. A device and system are disclosed in which different current switching pulses are applied to multiple groups of memory cells within the first and/or second operation units.