Memory Device Edge Block Load Balancing
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Solution Overview
Problem
In dynamic random access memory with an open bit-line architecture, edge memory cell blocks are not fully utilized due to incomplete connection to sense amplifiers, leading to wasted layout area, which is particularly problematic in small-size memories used in AI computing, increasing manufacturing costs.
Innovation Solution
The memory device incorporates edge blocks on both sides of the memory cell block, with strategically enabled word lines to balance loads between sense amplifiers, reducing the layout area required while maintaining load balance and improving sensing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sense amplifiers are disposed on two sides of each memory cell block in conventional memory, then the memory can be read and written through the sense amplifiers, but the two memory cell blocks at the edge cannot be fully utilized, resulting in wasted layout area
Solution Approach 1:
The edge blocks are configured to perform dual functions: they serve as memory cell blocks for data storage while simultaneously providing load balancing for the sense amplifiers. By enabling word lines in the edge blocks, they contribute to balancing the loads on both input ends of the sense amplifiers, thus eliminating the waste of layout area while maintaining proper sensing operation.
2Reliability
If edge blocks are fully utilized by enabling their word lines, then load balance between sense amplifier inputs is improved, but the complexity of managing enabled word lines increases
Solution Approach 1:
Instead of uniformly enabling all word lines in the edge blocks, the patent selectively enables specific word lines (e.g., alternating word lines or specific portions) in the edge blocks to match the enabled word lines in the adjacent memory cell blocks. This local quality approach achieves load balance while minimizing the number of enabled word lines, thus reducing control complexity.
Data Source
AI summary
A memory device includes at least one memory cell block, a first edge block, a second edge block, multiple first sense amplifiers, and multiple second sense amplifiers. The first edge block is coupled to multiple first word lines, where at least one of the first word lines receives an enabled first word line signal. The second edge block is coupled to multiple second word lines, where at least one of the second word lines receives an enabled second word line signal. The first sense amplifiers are disposed between the first edge block and the memory cell block. The second sense amplifiers are disposed between the second edge block and the memory cell block.