Addressable Test Chip Using Edge-Triggered Registers for High-Density DUT Testing

The patent implements multi-functional pads that can serve multiple DUTs through time-division multiplexing. Each pad is configured to be shared among multiple DUTs by controlling the switching circuitry, allowing a single pad to perform multiple testing functions sequentially. This resolves the contradiction by enabling high area utilization while maintaining test accuracy through proper signal routing and timing control.

The patent segments the addressing function by dividing the address space into multiple regions, each region corresponding to a specific group of DUTs. This segmentation allows the peripheral circuit to be organized in a modular fashion, where each module handles a subset of DUTs. The switching circuit is accordingly divided into multiple controlled switches, each managed by a portion of the address decode logic, reducing the complexity of any single module while supporting a large total number of DUTs.

The patent implements continuous testing by enabling the test apparatus to sequentially test multiple DUTs without interruption. The address register and switching circuit are coordinated to continuously cycle through the DUT array, allowing the test apparatus to maintain continuous operation. This continuous testing approach increases DUT density while managing test cycle time through efficient sequential access and parallel testing capabilities.

The patent implements preliminary actions by pre-configuring the address register with address spaces that map to specific DUT regions before testing begins. The switching circuit is pre-programmed with the correspondence between address signals and DUT selections. This preliminary configuration allows the test apparatus to rapidly access and test DUTs in high-density arrangements without time-consuming setup procedures, thereby improving failure detection rates while managing test period lengths through efficient pre-established testing pathways.