Digital Circuit Testing TRIZ Cases
- Modular Layer Blocks for Scalable Protocol Verification
Segmented layer blocks with transmit and receive routers provide controllability and modularity for pre-silicon functional verification.
- Remote Instrument Interface with Display for Connection Identification
A connection interface displays identifiers and measurement data to visually associate device under test points with host instrument connectors.
- AI Chip DFT Testing via Arithmetic Unit Segmentation
Segmenting artificial intelligence chips into identical arithmetic unit arrays reduces test time and power consumption while maintaining comprehensive coverage.
- Self Test Logic for Safety Critical Devices
Self test logic generates signal pairs to verify comparator circuits, resolving the trade-off between comprehensive fault detection and device complexity.
- Dual-Tester Semiconductor Package Testing System
A dual-test system conducts DC and functional tests on semiconductor packages using distinct contactor modules.
- Testable Circuit With Shadow Information Supply For Secure Debugging
A testable circuit switches to a shadow information supply during testing, allowing fault observation while preventing unauthorized access to confidential data.
- AC High Frequency Injection for DC Resistance Measurement Contact Checking
Injecting high frequency AC signals into the sense path allows continuous SMU operation while detecting open connections and minimizing measurement deviations.
- Integrated Impedance Measurement Device for SoC Internal Characterization
An integrated impedance measurement device embeds FFT processing within a system on chip to calculate electrical parameters directly from internal nodes.
- Scan Chain Unit Serial Signal Routing for DUT Testing
Serial signal lines route preset bits to scan chain units that store and output individual device control signals, reducing I/O pin requirements.
- Programmable Clock Delay Optimization for FPGA Timing
Automated EDA systems adjust programmable clock delays to optimize circuit timing slacks.
- Core-Only System Management Interrupt for Deterministic Debugging
A core-only periodic system management interrupt logs transactions at a virtual boundary to isolate the processor core.
- Scan Compression Clock Divider Phase Shifted Packing Logic
Clock divider generates phase shifted scan clocks for packing logic flip flops to produce slow scan outputs, handling slower scan outputs at optimal frequency.
- Fault Detection Feature Extraction in Semiconductor FDC Systems
Automated feature extraction from sensor profiles replaces subjective visual inspection with standardized ranking for reliable fault identification.
- Automatic Overclocking System for CPU and Cache Frequency Optimization
An automatic overclocking system tests CPU and cache frequency ranges to find stable operating points with minimal user input.
- Chip Testing Circuit Parallel Signal Pins Switch Power
A chip testing circuit uses parallel signal pins and switch circuits to power multiple chips simultaneously.
- Semiconductor Test Circuit for Internal Wire Delay Measurement
Test circuit measures internal signal propagation delays to configure programmable delay parameters, compensating for process voltage temperature variations.
- Adaptive Testing Engine for Integrated Circuit Test Cell Control
An adaptive testing engine generates commands to alter test cell parameters during integrated circuit evaluation.
- DUT Synchronization with ATE Check Cycle via SOP Indicator
A device under test transmits a start of packet indicator to synchronize with automated test equipment check cycles.
- Configurable Probe Blocks for Software Defined Network Monitoring
Configurable probe blocks embed monitoring logic within software defined networks to capture specific traffic characteristics without external hardware.
- Addressable Test Access Port with Command Capability
A control bit on the TDI signal enables device addressing during Run Test/Idle states.
- Automated Test Equipment Variable Signal Edge Selection
Test processor variably selects signal states from test vectors, resolving fixed edge bottlenecks in packet assembly and modification.
- Integrated Circuit Data Protection During Scan Mode
An integrated circuit uses a state machine to reset and scramble secure data in registers, preventing unauthorized access during scan mode transitions.
- Test Hardware Module for High-Speed Semiconductor Testing
Integrating signal generation into a compact interface unit shortens signal paths, enabling 24 Gb/s data rates while eliminating complex dedicated cabling.
- In-Chip Jitter Control via Adaptive PDN Impedance Modulation
A jitter control circuit modulates adaptive power delivery network impedance to generate specific current patterns for clock stability.
- Network Diagnosis Control via Message Identifier Verification
A diagnosis control device compares message identifiers to authorize disturbing tests within active networks.
- Dual-Ended Propagation Delay Measurement Without Common Phase Reference
Two independent measurement units transmit periodic signals through a device under test to calculate propagation delay via phase comparison.
- Built-in Self-Test Routing for Modular System-on-Chip Modules
A built-in self-test circuit routes test data through functional modules via an interconnect fabric to verify operational integrity.
- On-Wafer Test Circuitry with Tunable Threshold Voltage
Tunable threshold voltage FDSOI transistors drive test-only circuitry independently from functional blocks.