Self Test Logic for Safety Critical Devices
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Solution Overview
Problem
Safety critical devices, such as automotive radar systems and industrial controls, require built-in self-test mechanisms to identify faults in hardware logic and safety logic, but existing solutions are inadequate in ensuring comprehensive and efficient fault detection.
Innovation Solution
A system comprising a master module, compare module, comparators, and self-test logic that generates signal pairs to test both the circuit under test and the safety logic, using single cycle parallel bit inversion or multi-cycle serial bit inversion approaches to identify faults within a single cycle or multiple cycles, ensuring comprehensive coverage of safety logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If built-in self test mechanisms are implemented to identify faults in hardware logic, then fault detection capability is improved, but device complexity increases
Solution Approach 1:
The safety logic circuit performs self-testing by automatically generating test patterns and comparing its own outputs without requiring external test equipment. The circuit under test acts as both the device being tested and the testing apparatus, reducing overall system complexity while maintaining comprehensive fault detection capability.
Solution Approach 2:
The safety logic circuit is designed to serve multiple functions: it monitors hardware logic for faults during normal operation and simultaneously performs self-testing to detect faults within its own safety logic. This multi-functionality eliminates the need for separate test circuits, thereby reducing device complexity while improving reliability.
2Measurement precision
If comprehensive test mechanisms are implemented to identify faults in safety logic, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The self-test mechanism is divided into distinct functional segments: a test pattern generation unit that creates specific input patterns, a comparison unit that evaluates outputs against expected results, and a fault detection unit that identifies discrepancies. This segmentation allows each component to be optimized for its specific function, improving measurement precision while keeping individual components simple.
Solution Approach 2:
The circuit pre-calculates and stores expected output values for various input conditions during design. During operation, the self-test mechanism simply compares actual outputs against these pre-computed expectations, achieving high measurement precision without requiring complex real-time analysis circuits.
3Productivity
If single cycle parallel bit inversion is used for self test, then productivity is improved, but device complexity increases
Solution Approach 1:
The self-test mechanism dynamically switches between normal operation mode and self-test mode based on a control signal. In self-test mode, the circuit rapidly alternates through different test patterns and comparison operations within a single clock cycle. This dynamic operation achieves high test execution speed while using the same physical hardware, avoiding the need for dedicated high-speed test circuits.
4Device complexity
If multi-cycle serial bit inversion is used for self test, then device complexity is reduced, but productivity decreases
Solution Approach 1:
The self-test mechanism uses periodic clock cycles to systematically work through different test patterns and comparison operations. Each clock cycle performs a specific test function, and the sequence repeats for comprehensive coverage. This periodic approach allows the use of simpler sequential logic circuits while maintaining systematic fault detection, balancing device complexity and test execution speed.
Data Source
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AI summary
In described examples of self test logic for safety logic (100) in safety critical devices, the safety logic (100) includes comparator logic coupled to a master module (300) and a compare module (302) in a safety critical device, and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.