Chip Testing Circuit Parallel Signal Pins Switch Power
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Solution Overview
Problem
Existing memory testing apparatuses require a large number of pins and consume high power due to the need for extensive pin connections to test multiple memories, making them bulky and inefficient.
Innovation Solution
A chip testing circuit and method that uses a parameter measurement circuit, power supply circuits, and switch circuits, along with a control circuit to individually power and test each chip, reducing the number of pins required by connecting signal pins in parallel and controlling power supply through switch circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of pins are used to test multiple memories simultaneously, then the testing capability is improved, but the device size and power consumption are drastically increased
Solution Approach 1:
The power supply system is segmented into multiple independent power supply circuits, each capable of individually powering a single chip. This allows the testing apparatus to test multiple chips simultaneously with reduced total power consumption per chip, while maintaining the ability to test many chips by multiplexing the segmented power supply resources.
Solution Approach 2:
The switch circuits enable universal power distribution where any power supply circuit can serve any chip through controlled switching. This multi-functional switching architecture allows the same power supply resources to be dynamically allocated to different chips, reducing the total number of power supply channels needed while maintaining simultaneous testing capability.
2Productivity
If a large number of pins are used to test multiple memories simultaneously, then the testing capability is improved, but the device size is drastically increased
Solution Approach 1:
The power supply functionality is segmented into multiple independent power supply circuits that can be selectively activated. This segmentation allows the physical layout to be more compact since not all power supply circuits need to be simultaneously active or connected to all chips at once, reducing the overall device footprint while maintaining multi-chip testing capability.
Solution Approach 2:
The switch circuits introduce dynamic control over power supply connections, allowing the system to reconfigure which chips receive power from which power supply circuits. This dynamic switching capability enables a compact design where power supply resources are time-multiplexed across multiple chips, reducing the static physical space requirements compared to a fully parallel hardwired approach.
3Quantity of substance
If individual power supply circuits are connected to each socket with switch circuits, then the pin count is reduced, but the circuit complexity is increased
Solution Approach 1:
The switch circuits create a universal power distribution network where any power supply circuit can be connected to any chip socket through controlled switching. This multi-functional switching matrix allows the same set of power supply circuits to serve multiple chips in different configurations, reducing the total number of permanent pin connections needed while the switching logic manages the increased circuit complexity through systematic control.
Data Source
AI summary
A chip testing circuit and a testing method thereof are provided. The chip testing circuit includes a parameter measurement circuit, a plurality of power supply circuits, a plurality of switch circuits, and a control circuit. The plurality of power supply circuits respectively provide power supply to a plurality of chips carried by a plurality of sockets. Each switch circuit is electrically connected between one socket and one power supply circuit. The control circuit is connected in parallel to a plurality of signal pins of the plurality of chips carried by the plurality of sockets, so that when the control circuit outputs test data, all the chips can simultaneously receive the test data. When executing a parametric test mode, the control circuit controls one of the switch circuits to be turned on and controls the parameter measurement circuit to perform an electrical performance test on the chips.