Scan Chain Unit Serial Signal Routing for DUT Testing
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Solution Overview
Problem
The existing test methods for multiple devices under testing (DUTs) are inefficient due to the limited number of input/output (I/O) interfaces, which restricts the number of DUTs that can be simultaneously connected and tested, leading to reduced test efficiency.
Innovation Solution
A test method and system that utilize a serial signal line to send a preset signal with multiple bits to scan chain units, allowing each scan chain unit to store and output a signal corresponding to one DUT, thereby reducing the number of required I/O pins and enabling efficient individual testing of multiple DUTs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an individual chip selection line is provided for each DUT, then individual testing on each DUT is implemented, but the number of I/O interfaces is reduced and test efficiency decreases
Solution Approach 1:
The patent segments the chip selection control function by dividing it into multiple scan chain units, each controlling a subset of DUTs. This allows the test equipment to control multiple DUTs individually through a shared I/O interface by selecting specific scan chain units, thereby maintaining individual testing capability while reducing the number of required I/O interfaces.
Solution Approach 2:
The patent makes a single I/O interface serve multiple functions by using it to control multiple scan chain units that collectively manage multiple DUTs. The shared I/O interface can selectively activate different scan chain units based on the test requirements, enabling one interface to perform the work of multiple dedicated interfaces.
2Ease of operation
If each DUT occupies one I/O interface, then individual control is maintained, but the number of DUTs that can be tested simultaneously is limited
Solution Approach 1:
The patent merges multiple chip selection control functions into a unified scan chain unit structure that can be selectively activated. Multiple DUTs are grouped under shared scan chain units, allowing the system to maintain individual control capability while increasing the total number of DUTs that can be tested simultaneously through proper signal routing and control logic.
Solution Approach 2:
The patent introduces a hierarchical control dimension by organizing DUTs into groups managed by scan chain units, which are in turn controlled by the main test equipment. This multi-level control structure allows individual DUT control to be achieved through combination codes rather than dedicated one-to-one interfaces, effectively increasing the capacity in a dimensional sense.
3Productivity
If the number of I/O interfaces is increased to test more DUTs, then test capacity is improved, but device complexity and cost increase
Solution Approach 1:
The patent introduces scan chain units as intermediary components between the test equipment's I/O interface and the DUTs. These intermediaries multiply the effective control capacity of each I/O interface by implementing internal decoding and distribution logic, allowing one interface to control multiple DUTs without requiring proportional increases in interface quantity.
Solution Approach 2:
The patent uses scan chain units that can be replicated and configured in different patterns to control different groups of DUTs. Rather than creating unique dedicated interfaces for each DUT, the system uses configurable copies of the scan chain unit structure, reducing overall system complexity while maintaining test capacity.
Data Source
AI summary
The present invention provides a method, device, and system for testing devices under testing (DUTs). The method comprises: sending a scan activated signal and a synchronous clock signal via the second signal line, and sending a first preset signal via the serial signal line, wherein each bit of the first preset signal is transmitted to a corresponding scan chain unit in a sequence of serial connection of the plurality of scan chain units with according to the synchronous clock signal, the corresponding scan chain unit is one of the plurality of scan chain units connected serially and coupled to the plurality of DUTs via a third signal line; sending a scan deactivated signal via the second signal line, to deactivate the scan chain units from identifying and receiving the first preset signal; and sending a second preset signal via the second signal line, and sending a test signal via the first signal line.