Integrated Circuit Data Protection During Scan Mode
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Solution Overview
Problem
Integrated circuits face unauthorized access to secure data during scanning functions, as existing methods fail to effectively prevent data exposure during transition to and from test modes.
Innovation Solution
The integrated circuit is configured to enter test mode only after resetting and writing over secure data, using a state machine to provide a write-over instruction to data blocks, which scramble or erase data, and to bypass registers during scan mode, ensuring secure data is not accessible during scanning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scanning functions are performed on integrated circuits, then testing and debugging capabilities are improved, but unauthorized access to secure data becomes possible
Solution Approach 1:
The patent applies preliminary action by clearing secure data from scan-observable portions of the processor before entering test mode and clearing the scan chain again before exiting test mode. This proactive data removal prevents unauthorized access during scanning operations while maintaining testing functionality.
2Reliability
If secure data is cleared from scan-observable portions during mode transition, then data security is improved, but additional operations increase processing time
Solution Approach 1:
The patent implements periodic action by systematically clearing data at specific intervals - once before entering test mode and again before exiting test mode. This structured approach ensures security is maintained at critical transition points without requiring continuous monitoring or excessive clearing operations.
3Reliability
If scan chain access is denied during test mode, then secure data protection is improved, but scan chain functionality is reduced
Solution Approach 1:
The patent applies dynamics by dynamically controlling scan chain accessibility based on operational mode. The scan controller automatically denies access during test mode when secure data may be present and restores access during normal operation, adapting the system's security posture to current operational requirements without manual intervention.
Data Source
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AI summary
] Various example embodiments are disclosed. According to one example embodiment, an integrated circuit may include a mode block, a plurality of data blocks, and a reset node. The mode block may be configured to output a test mode signal, a scan mode signal, and a trigger signal based on a received data input. The plurality of data blocks may each include registers configured to store data, each of the plurality of data blocks being configured to write over at least some of the data stored in their respective registers in response to receiving a write-over instruction. The reset node may be configured to reset the registers based on receiving either a first reset input or a second reset input. The integrated circuit may be configured to enter a test mode, enter a scan mode, and exit the test mode.