AI Chip DFT Testing via Arithmetic Unit Segmentation
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Solution Overview
Problem
Traditional chip test methods are inefficient and costly for artificial intelligence chips due to their unique structure with numerous same arithmetic units, leading to increased test time, cost, and power consumption.
Innovation Solution
A method that determines whether an AI chip satisfies a test condition for arithmetic unit array or individual unit level, dividing units accordingly and using identical test logic circuits and vectors for each array or unit to perform Design for Test (DFT) tests, reducing test time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional chip test method is used on AI chips, then test coverage can be achieved, but test time increases significantly
Solution Approach 1:
The patent divides the AI chip into multiple identical arithmetic unit arrays, where each array contains multiple same arithmetic units. By segmenting the test into array-level and unit-level tests, the system achieves comprehensive coverage while reducing overall test time through parallel processing of identical structures.
Solution Approach 2:
The patent creates identical copies of test logic circuits and test vectors for each arithmetic unit array. Since all arrays are identical, a single test vector can be reused across multiple arrays, significantly reducing the total number of test vectors needed and thereby reducing test time while maintaining complete coverage.
2Reliability
If traditional chip test method is used on AI chips, then all arithmetic units can be tested, but test cost increases
Solution Approach 1:
The patent develops universal test logic circuits and test vectors that can be applied to all identical arithmetic unit arrays on the AI chip. This universal approach eliminates the need to develop separate test procedures for each array, significantly reducing test development cost and complexity while ensuring complete coverage of all arithmetic units.
Solution Approach 2:
By copying the same test logic circuit design across all arithmetic unit arrays and reusing identical test vectors, the patent reduces the overall test cost. The initial investment in creating the test methodology is amortized across all arrays, making the test process more cost-effective compared to traditional methods that would require custom test procedures for each unit.
3Reliability
If traditional chip test method is used on AI chips, then comprehensive testing is achieved, but test power consumption increases
Solution Approach 1:
The patent segments the testing process into hierarchical levels (array-level and unit-level tests), allowing power-efficient parallel testing of identical arithmetic unit arrays. This segmentation enables the test system to activate only the necessary portions of the chip at any given time, reducing overall power consumption while maintaining comprehensive test coverage.
Solution Approach 2:
The patent employs periodic testing patterns where identical test vectors are applied repeatedly to different arithmetic unit arrays in a systematic sequence. This periodic approach allows the test system to enter low-power states between test cycles and efficiently manage power delivery to only the actively tested arrays, thereby reducing overall test power consumption.
4Reliability
If traditional chip test method is used on AI chips, then all units are tested individually, but test efficiency decreases
Solution Approach 1:
The patent divides the AI chip into multiple identical arithmetic unit arrays and implements parallel testing at the array level. This segmentation enables simultaneous testing of multiple arrays using identical test vectors, dramatically improving test efficiency compared to sequential individual unit testing, while still achieving complete coverage of all arithmetic units through subsequent unit-level verification.
Solution Approach 2:
The patent merges the testing of multiple identical arithmetic unit arrays into a single parallel test operation by applying the same test vectors to all arrays simultaneously. This merging approach consolidates what would otherwise be separate sequential test processes into one efficient operation, significantly boosting test productivity while maintaining comprehensive coverage through the hierarchical test structure.
Data Source
AI summary
The present disclosure discloses a method and an apparatus for testing an artificial intelligence chip test, a device and a storage medium, and relates to the field of artificial intelligence. The specific implementation solution is: the target artificial intelligence chip has multiple same arithmetic units, the method includes: obtaining scale information of the target artificial intelligence chip; determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information; dividing all the arithmetic units into multiple same arithmetic unit arrays, and performing a DFT test on the arithmetic unit arrays, respectively, if it is determined that the test condition of the arithmetic unit array level is satisfied; performing the DFT test on the arithmetic units, respectively, if it is not determined that the test condition of the arithmetic unit array level is not satisfied.