Core-Only System Management Interrupt for Deterministic Debugging
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Solution Overview
Problem
Modern system-on-a-chip designs, with their increasing complexity and use of intellectual property blocks, face challenges in deterministic debugging due to nondeterministic components and lack of visibility into third-party IP blocks, making it impractical to perform clock-by-clock accurate replay of processor states for root cause analysis.
Innovation Solution
The implementation of a core-only periodic system management interrupt (PSMI) that treats the processor core as a deterministic domain and the rest of the system as nondeterministic, logging transactions at a virtual boundary defined between these domains, using a super queue and IDI ODLAT for inbound and outbound transaction collection, respectively, to minimize intrusiveness and ensure deterministic debug data collection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If clock-by-clock accurate replay of processor states is performed for deterministic debugging, then debugging precision is improved, but system complexity and cost increase significantly due to requiring entire system determinism
Solution Approach 1:
The system is segmented into a deterministic domain (processor core) and a nondeterministic domain (rest of the system including third-party IP blocks). By applying segmentation, the patent enables deterministic debugging to be applied only where needed (the core) rather than requiring entire system determinism, thus reducing complexity while maintaining debugging precision for the critical component.
Solution Approach 2:
Deterministic properties are applied locally to the processor core rather than uniformly across the entire system. The virtual boundary isolates the core as a deterministic domain with guaranteed clock-by-clock replay capability, while allowing nondeterministic components elsewhere in the system. This local application of determinism achieves debugging precision without system-wide complexity.
2Adaptability or versatility
If third-party IP blocks are integrated to enhance processor functionality, then adaptability is improved, but visibility for debugging deteriorates due to lack of access to internal operations
Solution Approach 1:
The virtual boundary acts as an intermediary between the deterministic core and nondeterministic third-party IP blocks. It captures and logs transactions (reads, writes, memory accesses) between the core and external components, providing debugging visibility into IP block operations without requiring direct access to their internal logic. This intermediary mechanism preserves adaptability while restoring measurement capability.
3Loss of information
If comprehensive transaction logging is implemented across the entire system, then debugging information completeness is improved, but intrusiveness and performance overhead increase
Solution Approach 1:
Transaction logging is segmented to occur only at the virtual boundary of the deterministic core rather than throughout the entire system. The super queue and IDI ODLAT log only core transactions (inbound and outbound), providing complete debugging information for the core while avoiding the intrusiveness of system-wide logging instrumentation.
4Reliability
If virtual boundary is introduced to separate deterministic and nondeterministic domains, then debugging determinism is improved, but device architecture complexity increases
Solution Approach 1:
The virtual boundary infrastructure (super queue, IDI ODLAT, transaction logging) is integrated into the existing core architecture and serves the deterministic debugging function automatically. The core's own transaction mechanisms are leveraged to provide debugging capability, rather than requiring separate external instrumentation. This self-service approach achieves debugging determinism with minimal additional architectural complexity.
Data Source
AI summary
An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.