Scan Compression Clock Divider Phase Shifted Packing Logic
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Solution Overview
Problem
In scan testing of semiconductor devices, the high inertial delay in ultra-low leakage (ULL) cell library based IOs limits the ability to drive scan operations at higher frequencies, resulting in slower scan outputs and longer test times, even with low-cost testers capable of higher clock frequencies.
Innovation Solution
A scan compression architecture that uses a clock divider to generate phase-shifted scan clocks and packing logic with flip-flops to produce kM slow scan outputs, allowing for efficient generation of slow scan outputs from M scan outputs and phase-shifted scan clocks, thereby addressing the frequency limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If ultra-low leakage (ULL) cell library based IOs are used to reduce leakage power, then power consumption is reduced, but scan operation frequency is limited to lower frequencies due to high inertial delay
Solution Approach 1:
The scan outputs are divided into multiple groups, with each group handled by a separate packing element. This segmentation allows parallel processing of scan outputs at different clock phases, effectively multiplying the output capacity without requiring higher clock frequencies, thus maintaining compatibility with ULL cells while increasing test throughput.
Solution Approach 2:
The patent introduces a time-multiplexing dimension by using multiple phase-shifted clocks (k phases) to handle scan outputs. Instead of trying to increase frequency in the time domain, the solution distributes scan output handling across multiple clock phases, effectively creating k parallel output channels from a single clock domain, thereby achieving kM outputs without proportionally increasing frequency.
2Loss of time
If scan operation frequency is increased to reduce test time, then test time is reduced, but ULL cell library based IOs cannot support higher frequencies due to high inertial delay on clock and data path
Solution Approach 1:
The patent employs periodic action by using multiple phase-shifted clocks that are periodically distributed across different time slots. Each packing element operates on a specific clock phase, and together they provide continuous periodic output at the required slower frequency, allowing test time to be optimized without exceeding the frequency capabilities of ULL cells.
Solution Approach 2:
The patent changes the clock frequency parameter from a single high frequency to multiple lower frequencies that are phase-shifted versions of each other. By transforming one high-frequency clock into k lower-frequency phase-shifted clocks, the system achieves the required output rate without requiring any single clock to exceed the ULL cell frequency capability, thereby reducing test time while respecting physical constraints.
3Speed
If kM slow scan outputs are generated from M scan outputs using phase-shifted clocks, then optimal scan frequency is achieved, but device complexity increases due to additional packing logic and flip-flops
Solution Approach 1:
Each packing element is designed as a universal module that can handle any scan output assigned to it, regardless of which clock phase is used. The packing elements are identical in structure (each containing k flip-flops), and they all perform the same function of capturing scan outputs and presenting them at the appropriate clock phase. This universality simplifies design and verification while achieving the required kM outputs.
Data Source
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AI summary
In described examples of a circuit (200) for testing an integrated circuit, the circuit (200) includes a scan compression architecture (205) driven by a scan clock (230) and generates M scan outputs (220), where M is an integer. A clock divider (232) is configured to divide the scan clock (230) by k to generate k number of phase-shifted scan clocks, where k is an integer. A packing logic (222) is coupled to the scan compression architecture (205) and generates kM slow scan outputs (224) in response to the M scan outputs (220) and the k phase shifted scan clocks. The packing logic (222) further includes M number of packing elements, and each of the M packing elements receives a respective one of the M scan outputs (220). Each packing element includes k number of flip-flops, and each of the k flip-flops in a packing element receives a respective one of the M scan outputs (220). Each flip-flop receives a respective one of the k phase-shifted scan clocks, such that each flip-flop generates a respective one of the kM slow scan outputs in response to the scan output and the phase-shifted scan clock.