Automated Test Equipment Variable Signal Edge Selection
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Solution Overview
Problem
Conventional test systems face difficulties in flexibility and efficiency due to the fixed number of signal edges in test vectors, leading to challenges in assembling packets, modifying patterns, and performing pre-execution modifications, especially when the natural protocol boundaries do not align with the selected number of edges.
Innovation Solution
An automated test equipment with a test processor that variably selects the number of signal states or transitions based on current instructions, allowing partial execution of test vectors and enabling flexible assembly and modification of test patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of signal edges in test vectors is fixed, then throughput is improved and data compression is achieved, but flexibility in assembling packets and modifying patterns deteriorates
Solution Approach 1:
The patent makes the number of signal edges dynamic by allowing the test processor to execute a variable number of edges from each test vector based on control signals. Instead of being fixed at compilation time, the edge count can be adjusted during runtime to match protocol boundaries and packet requirements, resolving the contradiction between fixed-edge efficiency and flexible assembly.
Solution Approach 2:
The invention changes the parameter of signal edge count from a fixed value to a variable parameter that can be modified during test execution. The test processor receives control signals that specify how many edges to execute from the current test vector, allowing adaptation to different packet sizes and protocol requirements while maintaining the underlying fixed mapping structure.
2Stability of the object's composition
If the number of signal edges in test vectors is fixed, then clock frequency stability is improved, but ease of modifying patterns during debug deteriorates
Solution Approach 1:
The patent segments the test vector execution into controllable portions by allowing the test processor to execute only the required number of edges from each vector. This segmentation enables independent modification of individual vector executions during debug without affecting the overall clock frequency stability, as each vector remains mapped to a fixed number of edges but only a subset is executed.
Solution Approach 2:
The invention implements partial action by allowing the test processor to execute only the necessary portion of each test vector's edges rather than the complete fixed set. This partial execution capability enables efficient pattern modification during debug, where only the required edges are applied while maintaining clock stability through the underlying fixed mapping structure.
3Quantity of substance
If test vectors are mapped onto a fixed number of signal edges, then data compression is achieved, but the need for padding operations increases
Solution Approach 1:
The patent extracts only the necessary number of edges from each test vector based on actual packet requirements. Instead of always executing the complete fixed set of edges and then discarding excess portions, the system extracts and executes only the required subset, eliminating the need for padding operations with unnecessary nop() instructions and reducing overall test time.
4Device complexity
If the number of signal edges is fixed for each test vector, then system simplicity is maintained, but pre-execution modification capability deteriorates
Solution Approach 1:
The patent prepares test vectors with a fixed mapping to a predetermined number of edges in advance, enabling efficient compilation and storage. During pre-execution modification, the system binds specific vector indices to packet positions and configures the variable edge count parameters before test run, combining preliminary preparation with flexible modification capability without significantly increasing system complexity.
Data Source
AI summary
An automated test equipment includes a test processor configured to provide a signal to a device under test on the basis of a sequence of instructions defining an evaluation of test vectors. The test processor is configured to map a test vector onto a set of signal states or signal transitions. Furthermore, the test processor is configured to variably select a number of signal states or signal transitions provided in the signal based on a current test vector in dependence on a current instruction.


