In-Chip Jitter Control via Adaptive PDN Impedance Modulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power supply induced jitter in chips is a significant issue due to the impedance variations in the power delivery network (PDN) and current sinking by drivers, causing clock jitter, which existing methods have not adequately addressed.
Innovation Solution
A jitter control circuit within a chip comprising an adaptive PDN, a current generator, and a controller that modulates impedance to generate currents with different patterns, using a look-up table to adjust impedance based on frequency to minimize clock jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PDN impedance is reduced to minimize supply voltage noise, then clock jitter is reduced, but the PDN becomes more complex to design and implement
Solution Approach 1:
The patent implements a dynamic impedance control mechanism where the PDN impedance is adjusted in real-time based on operating conditions. The controller modifies the impedance of the adaptive PDN according to the frequency and magnitude of currents drawn by drivers, allowing the system to maintain optimal clock stability across varying operational states rather than relying on a fixed low-impedance design.
Solution Approach 2:
The patent changes the impedance parameter of the PDN dynamically. By using a look-up table that maps current frequency and magnitude to optimal impedance values, the system adjusts the PDN impedance parameter adaptively. This allows the PDN to present different impedance characteristics under different operating conditions, resolving the contradiction between maintaining low impedance for clock stability and managing design complexity.
2Reliability
If additional current is drawn to reduce jitter (as in US 8,836,384 B1), then clock stability improves, but power consumption increases
Solution Approach 1:
Instead of continuously drawing additional current to suppress jitter, the patent changes the impedance parameter of the PDN dynamically. The controller adjusts the adaptive PDN impedance based on the actual current draw patterns and frequency content, allowing the system to maintain clock stability only when and where needed, rather than consuming extra power continuously.
Solution Approach 2:
The system uses the existing current draw information from normal operation to control the adaptive PDN impedance. The controller monitors the current patterns and autonomously adjusts the PDN impedance without requiring additional current injection, allowing the system to self-regulate clock stability using information already available from its normal operation.
3Reliability
If the PDN impedance is made frequency-dependent to optimize performance, then clock jitter is reduced, but the control system becomes more complex
Solution Approach 1:
The patent pre-calculates and stores optimal impedance settings in a look-up table before operation. The table contains pre-determined impedance values corresponding to various current frequency and magnitude combinations. During operation, the controller simply queries this pre-prepared table rather than performing complex real-time calculations, reducing the computational burden and control system complexity while maintaining frequency-dependent impedance optimization.
Solution Approach 2:
The patent replaces complex real-time impedance calculation mechanisms with a simpler lookup-based control approach. Instead of using sophisticated algorithms to compute optimal impedance in real-time, the system substitutes this with a pre-computed look-up table that maps operating conditions to optimal impedance settings, significantly simplifying the control system while preserving the frequency-dependent optimization benefits.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A jitter control circuit (100) within a chip (102) includes an adaptive PDN (1 10), a current generator (120) and a jitter generator (160). The adaptive PDN (110) is capable of being controlled/modulated to provide difference impedances. The current generator (120) is coupled to the adaptive PDN (110), and is arranged for receiving a supply voltage provided by the adaptive PDN (110) and generating currents with different patterns. The jitter generator is coupled to the adaptive PDN (1 10), and is arranged for generating a plurality of jitters corresponding to the currents with different patterns, respectively, according to the supply voltage provided by the adaptive PDN (110).