Testable Circuit With Shadow Information Supply For Secure Debugging
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Solution Overview
Problem
Existing electronic circuits face challenges in balancing circuit testing and debugging with the need to protect confidential data, as previous solutions either obstruct failure analysis or increase susceptibility to hacking.
Innovation Solution
A circuit design that includes a testable processor with a privileged information supply circuit, a test access circuit, and a multiplex circuit to switch between normal and test modes, using a shadow information supply circuit to prevent unauthorized access while allowing detailed testing and debugging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If direct test access is enabled to observe all circuit faults, then testing capability is improved, but confidential data protection deteriorates
Solution Approach 1:
The scan chain is segmented into a public portion for testing and a private bypass portion for secure data access. The bypass circuit can be selectively activated to access memory contents without going through the full scan chain, allowing fault observation while protecting confidential data from unauthorized retrieval.
Solution Approach 2:
A bypass circuit acts as an intermediary between the test access circuit and the memory containing confidential data. This intermediary allows controlled access to memory for testing purposes while preventing unauthorized access, mediating between the conflicting requirements of testing and security.
2Difficulty of detecting and measuring
If bypass circuit is used to access memory for testing, then fault analysis is improved, but data security deteriorates
Solution Approach 1:
The bypass circuit is made dynamic and controllable through a control signal from the test control circuit. The bypass can be selectively activated or deactivated based on testing requirements, allowing memory access when needed for fault analysis while maintaining security when bypass access is disabled.
Solution Approach 2:
The test control circuit receives feedback about the testing state and controls the bypass circuit accordingly. When testing requires memory access, the bypass is activated; when security is prioritized, the bypass is deactivated, creating a feedback-controlled system that balances testing and security needs.
3Object-affected harmful factors
If scan chain is cleared in test mode, then unauthorized data access is prevented, but debugging capability deteriorates
Solution Approach 1:
Instead of clearing the entire scan chain, only the public portion is used for testing while the private bypass portion remains intact for secure data access. This segmentation allows fault observation through the public scan chain while maintaining the ability to access confidential data through the private bypass circuit when needed for debugging.
Solution Approach 2:
Different portions of the scan chain are given different qualities: the public portion is cleared for testing to prevent unauthorized data access, while the private bypass portion maintains its data storage capability to enable secure debugging. This local differentiation allows both security and debugging requirements to be satisfied simultaneously.
Data Source
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AI summary
A circuit is operable in a normal operating mode and a test mode. The circuit contains a privileged information supply circuit (12) coupled to the testable circuit (10). A test access circuit (19) provides access to the testable circuit (10). A test control circuit (18) controls switching of the test access circuit (19) to the test mode. A multiplex circuit (16) couples the privileged information supply circuit (12) to the testable circuit (10) for access to privileged information in the normal mode. In the test mode the shadow information supply circuit (14) is coupled to the testable circuit (10) instead.