Adhesion Promoter Layer for Flip Chip Underfill Flow
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Solution Overview
Problem
In flip-chip packaging, the small gap between the IC die and the substrate due to Au stud collapse in Au—Au bonding technology hinders proper underfill flow, leading to reliability issues like underfill voids and adhesion problems without a solder mask layer, while removing the solder mask layer increases the gap but worsens adhesion.
Innovation Solution
A selective adhesive promoter layer is formed on the substrate surface under the IC die but not on the FC pads, increasing the gap for improved underfill flow and adhesion, using materials like silane coupling agents or surface roughening processes to prevent oxidation and enhance adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a solder mask layer is present on the substrate surface under the IC die, then adhesion of underfill to the substrate is improved, but the gap between the IC die and substrate is reduced hindering proper underfill flow
Solution Approach 1:
The patent removes the solder mask layer from the substrate surface in the die attach area to increase the gap between the IC die and substrate, enabling proper underfill flow. This extraction of the solder mask layer from the specific region resolves the contradiction by prioritizing gap size for underfill flow while accepting that adhesion must be maintained through alternative means (adhesion promoter layer or surface roughening) applied to the exposed metal surface.
2Length of moving object
If the solder mask layer is removed to increase the gap, then underfill flow is improved, but adhesion of underfill to the substrate surface deteriorates
Solution Approach 1:
The patent applies local quality by selectively removing the solder mask layer only in the die attach area where the IC die will be mounted, while potentially retaining it in other areas. This localized modification increases the gap precisely where needed for underfill flow without compromising adhesion in other regions. The adhesion promoter layer or surface roughening is also applied locally to the exposed metal surface in the die attach area to maintain adhesion properties.
3Strength
If adhesion promoter layer or surface roughening is applied to prevent oxidation and enhance adhesion, then adhesion is improved, but the gap is reduced
Solution Approach 1:
The patent employs parameter changes by modifying the surface properties of the substrate metal through adhesion promoter layer deposition or surface roughening processes. These treatments alter the surface energy, chemistry, or topography to enhance adhesion. The contradiction is resolved by applying these treatments to the exposed metal surface after solder mask removal, ensuring that the thin adhesion promoter layer or surface modification does not significantly reduce the already increased gap, while still providing the necessary adhesion enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces underfill voids and improves reliability by increasing the gap for better underfill flow without the adhesion issues associated with removing the solder mask layer, specifically benefiting Au—Au bonding but applicable to other solder interconnections as well.
Implementation Method 1
using materials like silane coupling agents or surface roughening processes to prevent oxidation and enhance adhesion
Implementation Method 2
using materials like silane coupling agents or surface roughening processes to prevent oxidation and enhance adhesion
Data Source
AI summary
A semiconductor device assembly (200) includes a workpiece (205) having a surface including a die attach region corresponding to regions under an integrated circuit (IC) die 210. The die attach region of workpiece (205) includes non-noble metal surfaces (215) and a plurality of flip chip (PC) pads at pad locations (214). A solder mask layer (207) is on a surface of the workpiece (205) outside the die attach region. The non-noble metal surfaces (215) in the die attach region include an adhesion promoter layer (221), wherein the adhesion promoter layer 221 is absent from the plurality of PC pads (214). An integrated circuit (IC) die (210) having a plurality of bumps (211) bonded in a flip chip arrangement to the workpiece (205). An underfill material (232) fills a space between the bumped IC die (210) and the workpiece (205).


