Adjustable Capacitance Multiplier Circuit for Low-Voltage Decoupling

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Solution Overview

Problem

Conventional capacitance multiplier circuits have limitations such as fixed capacitance values, high impedance requirements, and high power consumption, making them unsuitable for low voltage applications and requiring large circuit areas.

Innovation Solution

The integration of a capacitance multiplier circuitry comprising a capacitor, tunable resistor, and transconductance circuit, which allows for adjustable capacitance values without voltage drop and reduced power consumption, enabling effective noise suppression in integrated circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional capacitance multiplier circuits are used, then capacitance multiplication is achieved, but the circuit requires large circuit area and high power consumption

Engineering Contradiction:
Improvecapacitance valueVSAvoidcircuit area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent implements a dynamically adjustable capacitance multiplier circuit where the multiplication factor can be controlled in real-time through a control signal. This allows the circuit to adapt its capacitance value dynamically, providing high capacitance when needed while consuming minimal area and power during normal operation. The dynamic adjustment mechanism enables the circuit to achieve variable capacitance multiplication ratios without requiring multiple fixed capacitance circuits.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operating parameters of the capacitance multiplier circuit by introducing adjustable resistance values and control signals that modify the capacitance multiplication factor. By varying the resistance parameters and control voltage levels, the circuit can achieve different effective capacitance values from a single physical capacitor, thereby reducing the overall circuit area required compared to using multiple fixed capacitors.

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If conventional capacitance multiplier circuits are used, then capacitance multiplication is achieved, but the circuit consumes large amounts of power

Engineering Contradiction:
Improvecapacitance valueVSAvoidpower consumption
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The patent employs periodic switching action in the capacitance multiplier circuit, where the multiplication factor is adjusted periodically or on-demand rather than continuously. This periodic operation allows the circuit to achieve high capacitance values only when necessary for noise suppression, while remaining in a low-power state during normal operation. The periodic activation of the multiplication mechanism significantly reduces average power consumption.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The dynamically controllable capacitance multiplier adjusts its operation based on actual circuit needs, activating high capacitance multiplication only when noise suppression is required. This dynamic behavior enables the circuit to minimize power consumption by maintaining low-power operation during normal conditions while providing high capacitance values on-demand when power supply noise needs to be suppressed.

Inventive Principle:
Principle #15Dynamics

3Quantity of substance

If conventional capacitance multiplier circuits are used, then capacitance multiplication is achieved, but the circuit has fixed capacitance values and high impedance requirements

Engineering Contradiction:
Improvecapacitance valueVSAvoidcapacitance adjustability
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The patent implements a dynamically adjustable capacitance multiplier circuit where the multiplication factor can be controlled in real-time through a control signal. This allows the circuit to adapt its capacitance value dynamically, providing high capacitance when needed while consuming minimal area and power during normal operation. The dynamic adjustment mechanism enables the circuit to achieve variable capacitance multiplication ratios without requiring multiple fixed capacitance circuits.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent designs a universal capacitance multiplier circuit that can serve multiple functions: it provides high capacitance values for noise suppression, allows continuous adjustment of the capacitance value, and can adapt to different impedance requirements. The single circuit structure replaces multiple specialized circuits, achieving multi-functionality through programmable control and adjustable parameters.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution provides a wide range of adjustable capacitance values without increasing circuit area or power consumption, suitable for low voltage applications and improving power supply noise suppression.

Implementation Method 1

a transconductance circuit coupled to the capacitor and the adjustable resistance

Methodology Applied
Scientific EffectTransconductance:

Implementation Method 2

a capacitor having a first terminal coupled to the power supply line and having a second terminal

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 3

an adjustable resistance having a first terminal coupled to the second terminal of the capacitor and having a second terminal

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS12592681B2Capacitance multiplier for decoupling capacitor
Publication Date: 2026.03.31 APPLE INC
  • US12592681B2 patent drawing
  • US12592681B2 patent drawing
  • US12592681B2 patent drawing

AI summary

An integrated circuit may include one or more circuits coupled to capacitance multiplier circuitry. The capacitance multiplier circuitry may include a capacitor, fixed and tunable resistances, and a transconductance circuit. The tunable resistance can be adjusted to control the overall capacitance of the capacitance multiplier circuitry. The transconductance circuit may include a transistor having a drain terminal coupled to a first electrical component and a source terminal coupled to a second electrical component. The first electrical component may be a diode-connected transistor, a direct shorting wire, a resistor, an inductor, or a current source. The second electrical component may be a current source, a direct shorting wire, a resistor, an inductor, or another diode-connected device. Configured in this way, the capacitance multiplier circuitry can provide a large adjustable amount of capacitance without a voltage drop and without consuming a large amount of power.