Impedence Convertors TRIZ Cases

A tunable resistor and transconductance circuit multiply decoupling capacitance for low-voltage ICs without large area, voltage drop, or high power.

A transconductance circuit with tunable resistance boosts decoupling capacitance for low-voltage ICs without voltage drop or high power.

A single-VCII and OTA circuit simulates grounded positive or negative inductors while tuning impedance and frequency range with fewer components.

Acoustically coupled IDTs replace negatively coupled transformers to cut insertion loss and footprint in RF acoustic filters.

A single VCII+, OTA, and two impedances create tunable grounded positive and negative inductors with lower component count and wide frequency flexibility.

A single VCII+ and OTA circuit simulates grounded positive and negative inductors while reducing component count and widening frequency tuning.

A negative impedance converter cancels I/O pad capacitance to raise bandwidth while preserving signal integrity and ESD performance.

Cross-coupled differential pairs and CMFB networks create tunable negative impedance with better stability and practical IC implementation.

Current duplication circuits let a small IC capacitor mimic larger or smaller capacitance values, saving die area and avoiding discrete parts.

A gyrator-based reconfigurable gm-C filter handles non-contiguous carriers with one local oscillator, cutting receiver complexity and intermodulation.

A single-CFOA capacitance multiplier uses two resistors and a reference capacitor to simulate tunable positive or negative capacitance with less chip area.

Using GIC and gyrator-based higher-order paths, this filter widens the passband while sharply rejecting TX leakage and jammers.

Aging detection circuits raise IC operating voltage only when thresholds are reached, preserving reliability while avoiding excess early-life power use.

Serial crystal resonators and a CMOS negative impedance converter improve oscillator frequency stability while reducing acceleration and vibration sensitivity.

Received commands are checked for forbidden analog front-end states before reconfiguration, preventing corrupted data from causing invalid settings.

Using parasitic capacitance with a center-tapped inductor, this single-stage latch divider enables compact 120 GHz frequency division.

Calibration logic aligns timing across TSV-stacked chips by adjusting voltage and delay, improving data margins, power use, and reliability.

Parallel test-mode output over shared data channels lets stacked chips be tested simultaneously, cutting 3D semiconductor test time.

Dedicated through-chip lines and logical signal combining prevent temperature-data collisions in stacked semiconductor chips.

Cross-coupled differential transistor pairs and CMFB networks stabilize tunable non-Foster impedance conversion for wider antenna bandwidth.

A dedicated detection circuit uses an oscillator and logic to distinguish 3-pole and 4-pole audio jacks while reducing processor load and power use.

A multiplexed isolated serial link lets a gate driver carry richer control and status data while cutting redundant circuitry and complexity.

Dispatch logic routes messages without fixed addresses, enabling robust FPGA module communication and dynamic partial reconfiguration.

Coordinated module state switching prevents microcontroller interference that can corrupt ADC operation while enabling tighter chip layouts and lower power use.

End-mounted thermal insulation blocks heat from a stacked hot chip region, protecting adjacent semiconductor devices from thermal damage.

An on-die controller uses sensor feedback and body-bias adjustment to offset IC process and environmental variation while reducing power.

Varying electrode gap geometry creates a defect-free critical path, helping VSD layers switch reliably during low-energy transients.

A cascaded MOS backgate scheme reverse-biases parasitic diodes to cut leakage, extend hold time, and allow smaller sampling capacitors.

A negative impedance cell adds high-frequency gain peaking to a receiver equalizer, extending bandwidth to reduce ISI and improve BER.

By splitting and mirroring RC filter current, this circuit boosts effective capacitance without extra power or frequency-response instability.

A compensation circuit presents negative capacitance between antenna ports using coupled inductors and shunt acoustic resonators.

Varying gap distance across voltage switchable dielectric material concentrates current density along the critical path.

Unified digital control bits compensate both PMOS and NMOS drivers, minimizing impedance mismatch across PVT conditions while reducing layout area.