Receiver Equalizer With Negative Impedance for High-Bandwidth Gain

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Solution Overview

Problem

Conventional receiver equalizers lack the necessary high bandwidth and gain to effectively mitigate inter-symbol interference (ISI) and improve bit-error-rate (BER) in high-data-rate communications systems.

Innovation Solution

A high bandwidth, high gain receiver equalizer is designed with a pair of cascaded basic equalizer stages connected to a negative impedance cell, utilizing NMOS transistors and a negative impedance cell to extend bandwidth and achieve gain-peaking characteristics at high frequencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional equalizers are used, then the device complexity is low, but the bandwidth and gain are insufficient for high-data-rate applications

Engineering Contradiction:
ImprovebandwidthVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent changes the electrical parameters of the equalizer by introducing a negative impedance cell that provides negative resistance. This parameter change enables the equalizer to achieve higher bandwidth and gain by compensating for the bandwidth-limiting effects of package traces and load capacitances, thereby resolving the contradiction between maintaining low device complexity and achieving high bandwidth performance

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The negative impedance cell acts as an intermediary element between the equalizer stages. It provides negative resistance that compensates for the bandwidth limitations introduced by the transmission channel and load capacitances, enabling the equalizer to achieve high bandwidth without requiring complex circuit topologies

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If conventional equalizers are used, then the device complexity is low, but the gain is insufficient to mitigate inter-symbol interference

Engineering Contradiction:
Improvebit-error-rateVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces negative resistance as a key parameter change that enables high gain amplification. The negative impedance cell provides gain peaking at high frequencies, which directly improves the equalizer's ability to mitigate inter-symbol interference and reduce bit-error-rate in high-data-rate communications

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The equalizer employs dynamic gain control through the negative impedance cell that can adapt to different frequency components of the signal. The negative resistance provides frequency-dependent gain enhancement, allowing the equalizer to dynamically compensate for frequency-selective fading and inter-symbol interference

Inventive Principle:
Principle #15Dynamics

3Reliability

If bandwidth is increased to reduce inter-symbol interference, then the bit-error-rate improves, but the gain requirements become more demanding

Engineering Contradiction:
Improvebit-error-rateVSAvoidgain
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The patent converts the harmful effect of bandwidth limitation into a benefit by using the negative impedance cell to create gain peaking at high frequencies. The negative resistance compensates for the bandwidth-limiting effects of load capacitances and package traces, transforming what would be a performance limitation into an opportunity for enhanced high-frequency gain and improved bit-error-rate

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS7562108B2High bandwidth high gain receiver equalizer
Publication Date: 2009.07.14 TEXAS INSTRUMENTS INC
  • US7562108B2 patent drawing
  • US7562108B2 patent drawing
  • US7562108B2 patent drawing

AI summary

A receiver equalizer with a first equalizer unit having a basic equalizer stage and a negative impedance cell connected to the basic equalizer stage. Preferably the negative impedance cell has a pair of back to back transistors, and connected thereto a parallel resistor capacitor RC network. The basic equalizer stage has a pair of current sources; a pair of transistors arranged as a differential pair, each transistor connected to a different one of the current sources; and a degeneration impedance connected in between the two current sources, and the transistors, wherein the negative impedance cell is connected across the outputs of the pair of transistors.