Stacked Semiconductor Chip Lines for Collision-Free Temperature Signals

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Solution Overview

Problem

In semiconductor systems with stacked chips, delivering temperature information through a single through-semiconductor chip line can lead to collisions and imprecise information due to multiple chips transmitting different data, necessitating a reliable method for multiple lines.

Innovation Solution

The system employs a configuration where the uppermost chip transfers its information through an assigned line, and other chips logically combine and sequentially transfer internal information signals through corresponding through-semiconductor chip lines, ensuring accurate temperature information delivery to the controller in both normal and scan modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If multiple semiconductor chips deliver temperature information through a single through-semiconductor chip line, then the device complexity is reduced, but information collisions occur and delivery reliability deteriorates

Engineering Contradiction:
Improvenumber of through-semiconductor chip linesVSAvoidinformation delivery reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent divides the information delivery path into multiple separate through-semiconductor chip lines, with each line dedicated to carrying temperature information from specific chips. This segmentation prevents information collisions by ensuring that each chip's temperature data is transmitted through its own dedicated line, thereby improving delivery reliability without requiring complex multiplexing mechanisms.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If multiple semiconductor chips deliver temperature information simultaneously through the same line, then the manufacturing process is simplified, but information accuracy deteriorates due to collisions

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidtemperature information accuracy
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent assigns dedicated through-semiconductor chip lines to specific chips, creating separate transmission paths that eliminate information collisions. This segmentation approach maintains manufacturing simplicity by using straightforward one-to-one mappings between chips and lines, while ensuring accurate temperature information delivery from each chip without interference from other chips' data.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If a single through-semiconductor chip line is used for temperature information transfer, then the structure is simplified, but data transmission reliability deteriorates due to collisions among multiple chips

Engineering Contradiction:
Improvestructure simplicityVSAvoiddata transmission reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements multiple dedicated through-semiconductor chip lines, each assigned to carry temperature information from a specific chip. This segmentation strategy maintains structural simplicity by using direct point-to-point connections, while simultaneously improving data transmission reliability by eliminating collisions that would occur in a shared single-line configuration.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20120133423A1Semiconductor apparatus, semiconductor system, and method for outputting internal information thereof
Publication Date: 2012.05.31 SK HYNIX INC
  • US20120133423A1 patent drawing
  • US20120133423A1 patent drawing
  • US20120133423A1 patent drawing

AI summary

A semiconductor apparatus may include a plurality of through-semiconductor chip lines which pass through a plurality of stacked semiconductor chips. An uppermost semiconductor chip among the plurality of stacked semiconductor chips is configured to transfer its internal information signal to an assigned corresponding through-semiconductor chip line, and at least one semiconductor chip other than the uppermost semiconductor chip is configured to logically combine respective internal information signals transferred through through-semiconductor chip lines and their internal information signals and sequentially transfer resultant signals to assigned corresponding through-semiconductor chip lines. The at least one semiconductor chip other than the uppermost semiconductor chip logically combines the internal information signals transferred through the through-semiconductor chip lines from adjoining semiconductor chips and its internal information signals.