Differential Non-Foster Circuit Topology for Stable IC Integration
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Solution Overview
Problem
Existing Non-Foster Circuits, such as Negative Impedance Converters and Inverters, face instability issues and are difficult to implement in integrated circuit form, limiting their use in antenna impedance matching and metamaterial applications due to potential oscillations and the need for discrete transistors, which hinder mass production and practical application.
Innovation Solution
A differential circuit topology using two cross-coupled differential pairs of transistors, multiple current sources, Common-Mode Feedback networks, and tunable resistances allows for the creation of tunable floating negative inductance, capacitance, or resistance, separating bias networks from RF stability analysis and enabling IC implementation, thereby increasing bandwidth and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete transistors with bias networks are used to implement Non-Foster circuits, then the circuits can be constructed, but they result in lower performance, circuit instability, and difficulty in mass production
Solution Approach 1:
The patent replaces discrete transistor implementations with an integrated circuit implementation. The Non-Foster circuit is realized using integrated transistors (Q1-Q4) and passive components fabricated on a single semiconductor substrate, eliminating the need for discrete components and manual assembly. This substitution of discrete mechanical/electrical connections with integrated circuit technology enables mass production while maintaining circuit stability and performance.
2Device complexity
If single-ended NIC circuits are used, then the circuit structure is simpler, but they require bias current to flow through or around the load causing resonances and oscillations
Solution Approach 1:
The patent inverts the conventional single-ended NIC approach by implementing a differential circuit topology. Instead of having bias current flow through or around the load in a single-ended configuration, the differential structure (using differential pairs Q1-Q2 and Q3-Q4) allows bias currents to flow symmetrically through both sides of the circuit, canceling out unwanted resonances and oscillations while maintaining circuit stability.
3Reliability
If Non-Foster circuits are implemented with discrete components, then they can be demonstrated on the bench, but they cannot be feasibly produced commercially
Solution Approach 1:
The patent merges all circuit components - transistors Q1-Q4, resistors R1-R6, capacitors C1-C2, inductors L1-L2, and bias networks - into a single integrated circuit chip. This consolidation enables the circuit to be manufactured using standard IC fabrication processes, allowing commercial production while maintaining the stable differential topology that was previously only demonstrable with discrete components.
Data Source
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AI summary
A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as "non-Foster circuits." The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).