Electronically Tuned CFOA Capacitance Multiplier With Low Parasitics
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Solution Overview
Problem
Conventional Capacitance Multiplier circuits face issues such as high manufacturing costs, process and temperature dependence, excessive use of active and passive components, and parasitic noise, which affect frequency response and chip area utilization, especially in integrated circuits.
Innovation Solution
A Capacitance Multiplier circuit utilizing a single Current Feedback Operational Amplifier (CFOA) with minimal passive components, eliminating lossy terms and parasitic effects, and capable of simulating both positive and negative capacitance values without requiring critical component matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a physically large capacitor with high capacitance value is used, then the capacitance requirement is met, but the manufacturing cost becomes unfeasible and chip area increases
Solution Approach 1:
The patent creates a virtual copy of the capacitor function using active circuit elements (operational amplifier, resistors, and a small reference capacitor) instead of using a large physical capacitor. The simulated capacitor replicates the electrical behavior of a large capacitor through feedback mechanisms, achieving high effective capacitance without the physical footprint and cost of a real large capacitor.
Solution Approach 2:
The patent changes the operating parameters by using a small physical capacitor (C1) combined with active amplification to achieve a much larger effective capacitance value. The operational amplifier with gain β multiplies the small capacitance to produce an effective capacitance of Ceff = (1 + β)C1, transforming a small physical component into a large virtual capacitor.
2Area of stationary object
If Miller capacitance multiplier is used to avoid large physical capacitors, then chip area is reduced, but additional power consumption and circuit complexity increase
Solution Approach 1:
The operational amplifier in the patent serves multiple functions simultaneously: it acts as a voltage amplifier, a current source for the reference capacitor, and a feedback element to create the simulated capacitance. This multi-functionality reduces the need for separate dedicated components, thereby reducing overall circuit complexity compared to traditional Miller multipliers that require separate trans-impedance amplifiers.
3Quantity of substance
If conventional capacitance multiplier circuits are used, then large capacitance is achieved, but process and temperature variations cause capacitance value instability
Solution Approach 1:
The patent employs negative feedback through the operational amplifier to stabilize the effective capacitance value. The feedback mechanism compensates for variations in transistor parameters (β) and environmental conditions (temperature), maintaining a stable effective capacitance of Ceff = (1 + β)C1 even when component characteristics drift due to process or temperature variations.
4Device complexity
If operational amplifiers are used in capacitance multiplier circuits, then circuit simplicity is improved, but lossy terms and parasitic effects degrade performance
Solution Approach 1:
The patent uses a partial approach by employing only one operational amplifier instead of multiple amplifiers or complex current mirror circuits. This single op-amp configuration achieves the capacitance multiplication function with minimal passive components (two resistors and one reference capacitor), reducing the total number of components and thereby minimizing parasitic effects and noise while maintaining circuit simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a pure capacitance simulation with amplified values, reducing manufacturing costs and chip area usage while maintaining stability across ideal and non-ideal conditions, and improving frequency response.
Implementation Method 1
Capacitance multipliers can be grouped as voltage-based capacitance multipliers (e.g. Miller multipliers) and current-based capacitance multipliers. A current-based capacitance multiplier, a current through a capacitor is sensed, multiplied and fed back.
Data Source
AI summary
The present invention relates to a capacitance multiplier topology suitable for both positive and negative capacitance multiplication having a minimum configuration consisting of a current feedback amplifier (CFOA), two resistors and a reference capacitor, with each C-multiplier having a respective capacitance amplification constant k which is externally adjustable. Such a capacitance multiplier has less parasitic components, occupies a smaller chip area with higher simulated capacitance value.