Adjustable Frequency Doubler Calibration for Duty Cycle Correction
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Solution Overview
Problem
Designing frequency generation systems for portable RF devices that meet performance requirements for clock signals while balancing cost, board space, and power consumption is challenging, particularly due to issues with duty cycle errors in clock signals affecting sensitive circuitry like ADCs and PLLs.
Innovation Solution
An adjustable frequency doubling circuit that receives a first clock signal, generates a second clock signal with twice the frequency, and adjusts its duty cycle based on measured parameters to ensure a 50% duty cycle, thereby reducing spurious behavior and improving the performance of duty cycle-sensitive circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequency multiplication is performed using traditional methods (additional PLLs or DLLs), then the required clock frequencies are achieved, but the device complexity, board space, and power consumption increase
Solution Approach 1:
The patent combines frequency multiplication and duty cycle correction functions into a single integrated frequency doubler circuit. This merging eliminates the need for separate PLLs or DLLs, thereby reducing device complexity while achieving the required clock frequencies.
Solution Approach 2:
The frequency doubler circuit performs multiple functions simultaneously: it multiplies the input frequency by two and corrects the duty cycle to 50%. This multi-functionality reduces the overall system complexity by eliminating the need for separate frequency multiplication and duty cycle correction circuits.
2Speed
If frequency multiplication is performed using traditional methods (additional PLLs or DLLs), then the required clock frequencies are achieved, but the board space increases
Solution Approach 1:
The patent combines frequency multiplication and duty cycle correction functions into a single integrated frequency doubler circuit. This merging eliminates the need for separate PLLs or DLLs, thereby reducing device complexity while achieving the required clock frequencies.
3Speed
If frequency multiplication is performed using traditional methods (additional PLLs or DLLs), then the required clock frequencies are achieved, but the power consumption increases
Solution Approach 1:
The patent combines frequency multiplication and duty cycle correction functions into a single integrated frequency doubler circuit. This merging eliminates the need for separate PLLs or DLLs, thereby reducing device complexity while achieving the required clock frequencies.
4Speed
If duty cycle errors are present in the clock signal, then the frequency multiplication is achieved, but spurious behavior occurs in sensitive circuitry like ADCs and PLLs
Solution Approach 1:
The patent incorporates a duty cycle correction mechanism that uses feedback to adjust the duty cycle of the output clock signal. By monitoring the duty cycle and applying corrective adjustments, the circuit ensures a precise 50% duty cycle, thereby eliminating spurious behavior in sensitive circuitry.
Solution Approach 2:
The patent adjusts the duty cycle parameter of the clock signal to achieve a precise 50% value. By changing this critical parameter through the correction circuit, the system eliminates spurious responses while maintaining the frequency multiplication function.
Data Source
AI summary
In accordance with an embodiment, a method includes: receiving, by an adjustable frequency doubling circuit, a first clock signal having a first clock frequency; using the adjustable frequency doubling circuit, generating a second clock signal having a second clock frequency that is twice the first clock frequency; measuring a duty cycle parameter of the second clock signal, where the duty cycle parameter is dependent on a duty cycle of the first clock signal or a duty cycle of the second clock signal; and using the adjustable frequency doubling circuit, adjusting the duty cycle of the first clock signal or the second clock signal based on the measuring.