Adjustable Impedance SRAM Cell for Low Voltage Stability
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Solution Overview
Problem
Existing SRAM memory cells face challenges in achieving sufficient read and write noise margins, especially at low supply voltages, due to conflicting constraints on access transistors, leading to reduced tolerance and increased vulnerability to spurious switchings and indirect access noises, which affects the correct operation and storage reliability.
Innovation Solution
The solution involves varying the gain factor of the pull-up and pull-down branches of the NOT logic gates in SRAM memory cells dynamically by selectively introducing additional transistors in parallel, depending on the operation mode, to optimize read and write noise margins without compromising stability or increasing design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the conduction resistance of access transistors is increased to prevent spurious switchings during read operations, then read stability is improved, but write capability deteriorates due to insufficient switching strength
Solution Approach 1:
The access transistor function is segmented into two separate transistors: one optimized for read operations with higher conduction resistance to prevent spurious switchings, and another optimized for write operations with lower conduction resistance to ensure proper switching. This segmentation allows each transistor to be independently optimized for its specific function, resolving the contradiction between read stability and write capability.
Solution Approach 2:
An additional access transistor is introduced as an intermediary element to handle the write operation while the original access transistor maintains its read-optimized characteristics. This intermediary transistor mediates the write signal transmission, allowing the original transistor to maintain high read stability without compromising write capability.
2Reliability
If the conduction resistance of access transistors is decreased to improve write capability, then write capability is improved, but read stability deteriorates due to increased spurious switchings
Solution Approach 1:
The access transistor function is segmented into two separate transistors: one optimized for read operations with higher conduction resistance to prevent spurious switchings, and another optimized for write operations with lower conduction resistance to ensure proper switching. This segmentation allows each transistor to be independently optimized for its specific function, resolving the contradiction between read stability and write capability.
3Use of energy by moving object
If supply voltage is scaled down to reduce power consumption, then power consumption is reduced, but noise margins deteriorate leading to increased vulnerability to spurious switchings
Solution Approach 1:
Different parts of the access circuit are given different local qualities: one access transistor has higher conduction resistance for read stability, while the other has lower conduction resistance for write capability. This local differentiation allows the circuit to maintain adequate noise margins even at reduced supply voltages, as each transistor is optimized for its specific operational requirement.
Solution Approach 2:
The conduction resistance parameter of the access transistors is changed and differentiated: one transistor is designed with higher conduction resistance for read operations, while the other is designed with lower conduction resistance for write operations. This parameter change allows the memory cell to maintain sufficient noise margins at reduced supply voltages, enabling low-power operation without sacrificing reliability.
Data Source
AI summary
An embodiment of a memory device includes a plurality of memory cells; each memory cell includes a latch adapted to store an information bit. Said latch includes a first logic gate including a first input terminal and a first output terminal and a second logic gate including a second input terminal and a second output terminal. Said first input terminal is connected to said second output terminal and said first output terminal is connected to said second input terminal. The memory device further includes reading and writing means adapted to perform a read operation or a write operation of the information bit. Said first logic gate includes a pull-up branch coupled between a terminal for providing a supply voltage and the first output terminal, and a pull-down branch coupled between the first output terminal and a terminal for providing a reference voltage. Said second logic gate includes a pull-up branch coupled between a terminal for providing the supply voltage and the second output terminal, and a pull-down branch coupled between the second output terminal and a terminal for providing the reference voltage. Said memory device includes variation means adapted to selectively vary a gain factor of at least one between the pull-down branch and the pull-up branch of said first logic gate and second logic gate depending on the operation performed by the reading and writing means.