Digital Storage TRIZ Cases

A ReRAM programming technique transitions high resistance cells to low resistance state early in the operation cycle.

Resistors limit sink currents while a resonant oscillator drives write bit lines, minimizing power dissipation during data writes.

A switched capacitive unit cancels offset voltage errors during signal comparison, stabilizing data output driver impedance adjustments.

A dual-inverter memory device uses a control transistor to disconnect inverter stages during write operations.

Reset control unit detects gapless write operations and suppresses reset signals to prevent operation failures in synchronous memory devices.

A dual-mode memory system stacks logic and DRAM dice to increase data bandwidth via wide bus interfaces.

A drive device adjusts peri-voltage levels using NMOS and PMOS transistors to enable fast mode switching.

Probabilistic binary memory reduces storage resources and power consumption by encoding synaptic weights as switching probabilities in nonvolatile devices.

A DRAM sense amplifier circuit uses parallel branches with dynamic biasing to amplify bit line signals without reference cells.

A read assist circuit modulates wordline underdrive voltage via a bias circuit responding to process, voltage, and temperature conditions.

A memory device adjusts reference voltage levels during read operations to ensure accurate data retrieval.

An auto-refresh control circuit generates independent signals for dual-rank semiconductor memory devices.

A memory controller maintains latency type control signals using a write mask signal during pseudo static random access memory operations.

External redirection circuitry bypasses defective memory cells using wider internal data outputs.

Equalizing control circuit converts external potential to internal level for synchronized bit line equalization.

Distinct current pulses reduce write error rates by suppressing metastable domain formation during magnetization reversal.

A two-stage amplifier voltage generator uses preamplification and main amplification to drive load circuits accurately.

Temperature gradients induce spin currents to switch magnetic tunnel junctions, reducing current density requirements for viable MRAM.

A dynamic random access memory applies error correcting code only to rows with detected weak cells.

A semiconductor storage device uses a shared operational amplifier to control read and write operations through a single circuit path.

Ripple search groups discharge only matched match lines, reducing power consumption while maintaining high-speed search operations.

Segmented bit lines apply independent voltages to resolve parasitic resistance voltage drops during simultaneous cell operations.

A semiconductor device manages bank group selection signals and column control pulses to perform efficient data operations.

A gating circuit filters timing signals from memory devices using a dynamic window generated by a control signal.

Second semiconductor device generates start and oscillation signals based on reset inputs for memory initialization.

A voltage converting unit shifts synchronization data between power supply domains, eliminating phase lag caused by noise differences.

An RTA generation logic produces an enable signal one clock cycle before memory block access to activate the array supply voltage.

Merging code signal and test mode signal paths into a single global line via multiplexing reduces chip area while maintaining signal integrity.

A semiconductor memory device outputs row addresses during refresh operations to enable real-time verification of the process.

A memory cell varies pull-up and pull-down branch gain factors to optimize read and write noise margins.

Independent dummy word line drivers apply complementary stress biases to ensure equal stress on normal and dummy cells, preventing early product failures.

Integrating level shifting into the word line driver reduces substrate area and improves speed by eliminating separate circuits.

Segmenting FeFET functionality into dedicated pass and memory devices resolves linearity trade-offs during voltage pulses for online training.

A self-timed pulse input latch circuit enables asynchronous data handling in memory devices.

A memory section control circuit regulates word line driver voltage to minimize gate-induced diode leakage currents in inactive sections.

A semiconductor memory device uses count code signals to generate latch control signals for target address latching during burst refresh cycles.

A repair mask register selectively restores non-operational memory elements to reduce chip area overhead while maintaining high fault coverage.

A strobe signal buffer divides data strobe signals to generate internal strobe signals with specific phase differences.

A concentric semiconductor device stacks insulator and semiconductor layers around a central conductor to increase storage capacity.

A column decoder uses a driving voltage supply controller to manage power delivery for reduced leakage current.

Memristor-based TCAM bit cells replace SRAM transistors, increasing storage density and reducing power consumption.

Memory hub control block decodes command packets to trigger temperature requests from semiconductor devices.

A memory device employs a dummy bit line to share charge and stabilize bit line potential, preventing unintended switching element turn-on.

Bi-directional tracking circuits replace multiple uni-directional units to reduce device complexity while maintaining precise timing constraint accuracy.

Shared sense amplifier arrays manage external and refresh operations by storing addresses and varying values.

Pre-scanning detects environmental voltages from LCD polarity inversion, allowing the system to subtract these signals and prevent A/D converter saturation.

A magnetic memory device uses distinct heat absorption rates in nonmagnetic layers to stabilize magnetoresistive effect element properties.

A memory device refresh controller skips operations for accessed rows using flag information stored in registers.

A sensing unit detects individual memory cell characteristics to enable dynamic wear leveling adjustments.

Input circuit linearizes non-linear resistive memory current-voltage characteristics, resolving calculation accuracy deterioration in neural network training.