Semiconductor Memory Data Output Circuit Voltage Conversion
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Solution Overview
Problem
Conventional semiconductor memory apparatus data output circuits face issues with bit overlap due to differing noise characteristics between power supply voltage (VDD) and I/O power supply voltage (VDDQ), leading to phase lag in output data "DQ" when these voltages have different levels.
Innovation Solution
A data output circuit with a clock synchronization unit driven by power supply voltage, a voltage converting unit that converts synchronization data between power supply and ground voltage to I/O power supply and ground voltage, and a data output driver driven by I/O power supply voltage, ensuring stable output data regardless of voltage differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the clock synchronization unit is driven by power supply voltage (VDD) and the data output driver is driven by I/O power supply voltage (VDDQ), then the data output circuit can operate with separate power sources, but phase lag occurs between synchronization data and output data when voltage levels differ due to different noise characteristics
Solution Approach 1:
A voltage conversion unit is introduced as an intermediary component between the clock synchronization unit (driven by VDD) and the data output driver (driven by VDDQ). This unit converts the first synchronization data from the VDD voltage level to the VDDQ voltage level, ensuring proper phase alignment and signal integrity when the two power sources have different voltage levels due to different noise characteristics.
2Adaptability or versatility
If voltage levels between VDD and VDDQ differ, then the circuit can tolerate power supply variations, but bit overlap occurs in the output data due to phase misalignment
Solution Approach 1:
The voltage conversion unit acts as a mediator that adapts signals from one voltage domain (VDD) to another voltage domain (VDDQ). This allows the system to tolerate variations in power supply voltages while maintaining precise bit alignment in the output data by ensuring that synchronization data and output data operate at the same voltage level.
3Device complexity
If the data output driver directly processes synchronization data without voltage conversion, then the circuit structure is simpler, but phase lag causes data output errors when power supply voltages differ
Solution Approach 1:
While adding a voltage conversion unit increases circuit complexity, it is a necessary intermediary to ensure data output accuracy when VDD and VDDQ have different voltage levels. The unit converts synchronization data to the appropriate voltage level before it reaches the data output driver, preventing phase lag and bit overlap errors.
Solution Approach 2:
The voltage conversion unit changes the voltage parameter of the synchronization data from VDD level to VDDQ level. This parameter transformation ensures that the data signal is compatible with the driver's operating voltage, maintaining data output accuracy despite differences in power supply characteristics.
Data Source
AI summary
A data output circuit of a semiconductor memory apparatus can include a clock synchronization unit (which is driven by a power supply voltage) that can be configured to receive data and output first synchronization data and second synchronization data in synchronization with a clock; a voltage converting unit that can be configured to convert the first and second synchronization data, which can swing between the power supply voltage and a ground voltage, into first and second converted data, which can swing between an I/O power supply voltage and the ground voltage; and a data output driver, which is driven by the I/O power supply voltage, for outputting the first converted data and the second converted data as output data.