Semiconductor Memory Impedance Adjustment via Offset Cancellation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor memory devices face challenges in accurately adjusting the output impedance of data output drivers during OCD/ODT calibration control, leading to potential offset errors and impedance variations, which can affect data transmission reliability.
Innovation Solution
A semiconductor memory device is designed with a reference signal generating unit, a comparing unit that includes a voltage comparator and a switched capacitive unit to remove offset voltage, and a latch unit to ensure accurate comparison and impedance measurement, allowing for precise adjustment of pull-up and pull-down impedances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a voltage comparator is used to compare signals for impedance calibration, then the calibration function can be implemented, but offset voltage errors occur in the comparison result
Solution Approach 1:
A switched capacitive unit is introduced as an intermediary component between the voltage comparator and the rest of the circuit. This unit includes capacitors and switches that temporarily store and process voltage signals, enabling offset voltage cancellation through charge redistribution before the final comparison is made.
Solution Approach 2:
The circuit implements feedback by using the output of the voltage comparator to control the switched capacitive unit, which then adjusts the input signals to the comparator. This feedback mechanism continuously corrects offset voltage errors until the comparison result stabilizes.
2Reliability
If impedance adjustment is performed during OCD/ODT calibration control, then output impedance can be optimized, but noise interference affects the adjustment accuracy
Solution Approach 1:
The switched capacitive unit performs preliminary action by pre-processing the voltage signals and canceling offset voltages before they reach the voltage comparator. This preliminary processing ensures that the comparison is made on clean, noise-free signals, improving adjustment accuracy.
Solution Approach 2:
The switched capacitive unit acts as a mediator that isolates the voltage comparator from noise in the rest of the circuit. By buffering and conditioning the signals through capacitive coupling and switch control, it protects the comparator from noise interference during the critical impedance adjustment process.
3Device complexity
If the comparing unit directly compares input signals for impedance calibration, then the calibration process is simple, but offset voltage and noise interfere with accurate comparison
Solution Approach 1:
The switched capacitive unit is inserted as an intermediary between the input signals and the voltage comparator. It includes capacitors that temporarily store signal charge and switches that control the timing of charge transfer, enabling precise comparison while filtering out offset voltages and noise.
Solution Approach 2:
The switched capacitive unit performs preliminary action by pre-conditioning the input signals before they reach the comparator. It cancels offset voltages through charge redistribution and ensures that only clean, accurate signals are compared, significantly improving measurement precision without requiring complex filtering circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively removes offset errors and stabilizes impedance adjustments, ensuring reliable data transmission by accurately comparing input signals and adjusting output impedance without noise interference.
Implementation Method 1
a switched capacitive unit for receiving the reference signal and the test signal to remove an offset voltage occurred in the positive input node, the negative input node, the positive output node and the negative output node of the voltage comparator
Data Source
AI summary
An apparatus for comparing inputted signals by removing an offset voltage during adjusting an output impedance of a semiconductor memory device, includes a voltage comparator for comparing a first input signal applied to its positive input node with a second input signal applied to its negative input node to output a first output signal to its positive output node and its second output signal to a negative output node; a switched capacitive unit for removing an offset voltage occurred in the positive input node, the negative input node, the positive output node and the negative output node of the voltage comparator; and a latch unit for latching the first output signal and the second output signal.