Memory Redundancy via External Data Line Redirection
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Solution Overview
Problem
Conventional memory systems require complex test operations to detect defective cells, especially when redundant cells are involved, and non-repairable memories lack internal redundancy, making it difficult to simplify testing and provide effective cell replacement.
Innovation Solution
A memory system with a built-in self-test (BIST) circuit and external redirection circuitry, where the memory has a larger data output bit width than the system, allowing for simultaneous testing of all memory cells and redirecting data lines to bypass defective cells, thereby simplifying the test and repair process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory systems use internal redundancy for defective cell replacement, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the redundancy functionality from the internal memory structure and places it in external circuitry. The memory device itself remains simple without internal redundant rows or columns, while external circuitry provides the replacement capability through data line redirection, thus improving reliability without increasing memory device complexity
Solution Approach 2:
The patent introduces external redirection circuitry as an intermediary between the memory device and the system. This intermediary contains the defective cell information and controls data line redirection to bypass defective cells, separating the redundancy management function from the memory structure itself
2Measurement precision
If memory systems perform complex test operations to detect defective cells, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent performs preliminary testing of all memory cells during manufacturing using built-in self-test (BIST) circuitry. Defective cells are identified and recorded in advance, allowing the memory to be fully operational without requiring complex test operations during system operation or maintenance
Solution Approach 2:
The patent implements built-in self-test (BIST) circuitry within the memory device that automatically tests its own cells without requiring external test equipment. The memory tests itself during manufacturing, identifies defective cells, and configures redirection paths autonomously, eliminating time-consuming external testing procedures
3Device complexity
If non-repairable memories are used to simplify design, then device complexity is reduced, but reliability deteriorates
Solution Approach 1:
The patent makes simple non-repairable memories universal by adding external redundancy circuitry that can handle defective cells. The same memory device design can be used in applications requiring reliability, with the external circuitry providing the repair functionality, thus eliminating the need for different memory designs based on reliability requirements
Solution Approach 2:
The patent moves the redundancy functionality from the internal memory structure to an external dimension. Instead of having redundant rows or columns within the memory array, the system uses external circuitry with data line redirection capability, adding redundancy in a different dimensional space outside the memory device
Data Source
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AI summary
A memory system includes a memory that provides digital data and a built-in self-test (BIST) circuit for testing the memory for determining defective storage units of the memory. The memory system has a data output for providing data from the memory to an external system. The data output of the memory system has a first bit width. The memory has a data output that has a second bit width that is greater than the first bit width. The BIST circuit has a data input that is of the second bit width.