Semiconductor Memory Global Line Multiplexing for Chip Area Reduction
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Solution Overview
Problem
Conventional semiconductor memory devices require numerous global lines for impedance calibration and test mode signals, leading to increased chip area due to the need for separate lines for code signals and test mode signals.
Innovation Solution
A semiconductor memory apparatus with a common global line control block that selectively outputs either a code signal or a test mode signal to a common global line based on a line calibration signal, allowing for interchangeable use of code signal lines and test mode signal lines, thereby reducing the number of global lines needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate lines are used for code signals and test mode signals, then signal integrity and reliability are improved, but chip area increases due to numerous global lines
Solution Approach 1:
The patent merges the code signal lines and test mode signal lines into a single common global line. A multiplexer selectively connects either the code signals (PCODE, NCODE) or test mode signals (TM) to this common line based on the operation mode, thereby reducing the total number of global lines and chip area while maintaining signal integrity through dedicated transmission paths when needed
Solution Approach 2:
The common global line is designed to serve multiple functions: it can transmit code signals during normal operation and test mode signals during testing. The multiplexer enables this line to be universally used for different signal types, eliminating the need for separate dedicated lines for each signal category
2Adaptability or versatility
If numerous global lines are used for code signals and test mode signals, then functionality and versatility are improved, but device complexity increases
Solution Approach 1:
Multiple signal lines (code signal lines and test mode signal lines) are merged into a single common global line. The multiplexer manages the selective connection of different signal sources to this common line, reducing the overall line count and simplifying the global interconnect structure while preserving the ability to transmit various signal types
Solution Approach 2:
The multiplexer acts as an intermediary device that manages the connection between multiple signal sources (code signals and test mode signals) and the common global line. It selectively routes the appropriate signal to the common line based on the current operation mode, thereby simplifying the overall system architecture while maintaining full functionality
Data Source
AI summary
A semiconductor memory apparatus includes: a line calibration unit configured to selectively output one signal from the group of code signals for calibrating termination resistance values and test mode signals for testing a chip of the semiconductor memory apparatus to a common global line based on the level of a line calibration signal.