ReRAM Programming Sequence for Leakage Current Reduction
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Solution Overview
Problem
Resistive RAM (ReRAM) based memories suffer from parasitic leakage currents during programming, which increase power consumption, reduce read operation accuracy, and limit programming rate and sequence due to the resistive nature of memory cells.
Innovation Solution
Optimizing the programming sequence by identifying subsets of memory cells in low and high resistance states and programming them in a reset-then-set process, where cells in the high resistance state are transitioned to low resistance first, to minimize leakage currents and optimize power consumption and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional programming sequence is used, then programming operation can be completed, but parasitic leakage currents increase power consumption and reduce read operation accuracy
Solution Approach 1:
The patent applies preliminary action by first resetting all memory cells to a known initial state (high resistance state) before performing the actual programming operation. This preliminary reset action ensures that no parasitic leakage currents from previously programmed cells interfere with the subsequent programming operation, thereby reducing power consumption and improving read operation accuracy.
Solution Approach 2:
The patent segments the programming operation into distinct phases: a reset phase where all cells are first reset to high resistance state, followed by a programming phase where selected cells are programmed to low resistance state. This segmentation separates the conflicting operations of reading/writing from the programming operation, eliminating interference and reducing leakage currents.
2Productivity
If all memory cells are programmed simultaneously, then programming rate is maximized, but parasitic leakage currents from high resistance cells limit programming capability
Solution Approach 1:
The patent performs a preliminary reset of all memory cells to high resistance state before programming. This preliminary action eliminates the harmful parasitic leakage currents that would otherwise be generated by high resistance cells during simultaneous programming, enabling higher programming rates without interference.
Solution Approach 2:
The patent converts the potentially harmful high resistance state of memory cells into a beneficial initial condition. By resetting all cells to high resistance state first, the patent eliminates parasitic leakage currents that would interfere with programming, thereby enabling more efficient and faster programming operations.
3Use of energy by stationary object
If programming sequence is not optimized, then implementation is simple, but power consumption increases due to unminimized leakage currents
Solution Approach 1:
The patent implements a simple yet effective preliminary reset action before programming. This preliminary action, while adding a step, significantly reduces power consumption by eliminating parasitic leakage currents. The complexity is justified by the substantial power savings achieved through this preliminary conditioning of the memory cell array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces the dominant leakage current in ReRAM memories, improving write performance and power efficiency by prioritizing the transition of high resistance cells to low resistance cells during programming.
Implementation Method 1
A variety of materials show reversible resistance-change or resistance-switching behavior in which the resistance of the material is a function of the history of the current through, and/or voltage across, the material.
Data Source
AI summary
A programming technique for a set of resistance-switching memory cells such as ReRAM cell involves programming the low resistance cells to the high resistance state (in a reset process) early in a programming operation, before programming the high resistance cells to the low resistance state (in a set process), to minimize losses due to leakage currents. The reset process can be performed in one or more phases. In some cases, a current limit is imposed which limits the number of cells which can be reset at the same time. Initially, the cells which are to be reset and set are identified by comparing a logical value of their current resistance state to a logical value of write data. If there is a match, the cell is not programmed. If there is not a match, the cell is programmed.