DRAM Sense Amplifier Circuit Using Complementary Bit Line Reference
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional DRAMs using reference cells for ground precharge increase memory bulk, require additional transistors, and prolong read cycles due to charge balancing time, and existing sense amplifiers with parallel branches do not effectively address these issues.
Innovation Solution
A DRAM sense amplifier design that eliminates the need for reference cells by using a configuration with P-channel transistors in series and additional parallel transistors for dynamic biasing during read cycles, connected to bit lines without requiring precharged reference cells, allowing for improved sensitivity and reduced complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If reference cells are used for ground precharge, then the reading speed is improved, but the memory bulk increases and additional transistors are required
Solution Approach 1:
The invention extracts and eliminates the reference cells from the DRAM architecture. By removing the reference cell component entirely and replacing it with a sense amplifier that uses the complementary bit line as a natural reference, the patent reduces memory bulk while maintaining fast read performance. The sense amplifier directly compares the bit line voltage against the complementary bit line (which is precharged to ground) without requiring separate reference storage elements.
Solution Approach 2:
The complementary bit line serves multiple functions: it acts as both a data transmission line and a reference voltage source for the sense amplifier. By making the complementary bit line serve dual purposes, the invention eliminates the need for separate reference cells and additional transistors, thereby reducing memory bulk while maintaining fast read capability.
2Speed
If reference cells are used for ground precharge, then the reading speed is improved, but the device complexity increases due to additional transistors
Solution Approach 1:
The invention removes the reference cell structure and its associated control transistors from the DRAM design. The sense amplifier is configured to use the complementary bit line directly as a reference, eliminating the need for additional transistors that would be required to control reference cell access and charge sharing.
Solution Approach 2:
The complementary bit line is designed to serve dual functions: data transmission and reference voltage provision. This multi-functionality eliminates the need for separate reference cell control circuitry and additional transistors, thereby reducing device complexity while maintaining fast read performance.
3Speed
If reference cells are used for ground precharge, then the reading speed is improved, but the read cycle duration increases due to charge balancing time
Solution Approach 1:
By removing the reference cell mechanism, the invention eliminates the charge balancing step that would otherwise be required. The sense amplifier directly compares the bit line voltage against the complementary bit line voltage without needing to transfer or balance charges between reference and data cells, thereby shortening the read cycle duration.
Solution Approach 2:
The complementary bit line is precharged to ground voltage in advance, preparing it to serve as a reference for the sense amplifier comparison. This preliminary precharging action eliminates the need for charge balancing during the read cycle, as the reference voltage is already established and ready for immediate comparison with the data bit line voltage.
4Measurement precision
If additional transistors are added for parallel branch configuration, then the sensitivity is improved, but the device complexity increases
Solution Approach 1:
The sense amplifier uses the complementary bit line to serve dual purposes: as a data transmission line and as a reference voltage source. This multi-functionality allows the amplifier to achieve high sensitivity through differential comparison without requiring additional transistors for reference cell control, thereby improving sensitivity while avoiding increased device complexity.
Data Source
AI summary
A sense amplifier of a DRAM includes, in series between two terminals of application of a supply voltage, at least one first transistor of a first channel type, and an amplification stage formed of two parallel branches each including a second transistor of the first channel type in series with a transistor of a second channel type. The gates of the transistors of a same branch are connected to the junction point of the transistors of the other branch. Each branch including at least one first additional transistor of the first channel type in parallel with at least each second transistor of the first channel type.