Auto-Refresh Control Circuit for Independent DRAM Rank Operations
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Solution Overview
Problem
Current 2-rank DRAM devices face challenges in performing auto-refresh operations simultaneously or individually when the ranks operate independently, requiring effective control circuits to manage chip selection signals and refresh information.
Innovation Solution
An auto-refresh control circuit is designed with a control signal generating section and an auto-refresh signal generating section to enable simultaneous or individual auto-refresh operations based on information combination signals, chip selection signals, and command signals, allowing each rank to perform auto-refresh operations independently or cooperatively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two ranks operate independently with individual auto-refresh control, then operational flexibility is improved, but control circuit complexity increases
Solution Approach 1:
The control circuit is segmented into two independent control paths, each capable of generating auto-refresh signals for individual ranks. This allows each rank to be controlled separately while sharing common refresh timing logic, achieving operational flexibility without proportionally increasing overall circuit complexity.
Solution Approach 2:
The control circuit is designed with universal components that can serve multiple functions: the same refresh counter and control logic can manage either single-rank or dual-rank operations, and can switch between cooperative and independent auto-refresh modes without requiring completely separate control paths.
2Productivity
If two ranks perform auto-refresh simultaneously, then memory refresh efficiency is improved, but control signal management becomes more complex
Solution Approach 1:
The patent merges the refresh control logic for both ranks into a unified control structure. A single refresh counter generates timing signals that are distributed to both ranks, and control signals are combined through logic gates that enable simultaneous auto-refresh operations while maintaining coordinated timing across both memory ranks.
3Adaptability or versatility
If chip selection signals are used to select independent ranks, then memory access flexibility is improved, but signal routing complexity increases
Solution Approach 1:
The control circuit introduces intermediary logic elements (such as control signal generating sections and logic gates) that mediate between the chip selection signals and the auto-refresh signal generation. These intermediaries translate chip selection states into appropriate control signals for each rank, enabling flexible memory access while simplifying the overall signal routing architecture.
Data Source
AI summary
An auto-refresh control circuit includes a control signal generating section configured to simultaneously or individually enable first and second control signals in response to an information combination signal having refresh information and operation mode information and first and second chip selection signals, and an auto-refresh signal generating section configured to generate first and second auto-refresh signals in response to a plurality of command signals and the first and second control signals.