Semiconductor Memory Refresh Verification via Real-Time Row Address Output
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Solution Overview
Problem
Semiconductor memory devices face challenges in accurately verifying and analyzing refresh operations in real-time, making it difficult to detect errors and ensuring data integrity due to significant time requirements for verification and limited real-time error recognition.
Innovation Solution
A semiconductor memory device design that includes address storage circuits, output control circuits, and strobe signal generation, enabling the output of row addresses for each bank during refresh operations, allowing for real-time verification and analysis of the refresh process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data reading is performed after refresh operation completion to verify refresh normality, then refresh operation verification is achieved, but verification time is significantly increased and real-time error detection is difficult
Solution Approach 1:
The patent applies preliminary action by capturing and storing the row address during the refresh operation itself, before the operation completes. The address storage circuit records the row address when the refresh command is active, enabling immediate verification without waiting for refresh completion. This transforms the verification process from a post-operation check to a real-time monitoring capability.
Solution Approach 2:
The patent introduces an intermediary mechanism (address storage circuit and output control circuit) that bridges the refresh operation and verification processes. Instead of directly reading data after refresh, the system uses the stored row address as an intermediary to identify and verify the refreshed location, enabling faster and more efficient verification.
2Reliability
If traditional data reading method is used to verify refresh operation, then refresh verification is possible, but real-time error recognition is difficult and analysis capability is limited
Solution Approach 1:
The patent implements feedback by continuously monitoring and outputting the row address during refresh operations. This creates a real-time feedback loop where the system can immediately detect if a row address is being refreshed when it shouldn't be, or if refresh operations are occurring in unexpected sequences. The feedback mechanism enables proactive error detection rather than reactive verification.
Solution Approach 2:
The patent replaces the mechanical data reading process with an electronic address output and comparison system. Instead of physically reading data from memory cells after refresh, the system electronically outputs and analyzes row addresses, enabling faster and more automated error detection through digital signal processing and comparison logic.
3Use of energy by moving object
If refresh operation is performed without real-time monitoring, then power consumption is reduced, but error detection and data integrity verification are compromised
Solution Approach 1:
The patent applies self-service by using the existing refresh command signal and internal address generation logic to automatically capture and output row addresses during refresh operations. The system monitors itself without requiring external monitoring equipment or additional power-intensive verification routines. The address storage circuit leverages the already-present refresh control signals to perform self-diagnosis and self-verification.
Data Source
AI summary
A semiconductor memory device may include a plurality of banks; a plurality of address storage circuits respectively corresponding to the plurality of banks, and suitable for storing refresh addresses of corresponding banks; an output control circuit suitable for, based on a refresh command signal and a test mode signal, generating an output clock and selectively outputting, as output data, a refresh address outputted from any one of the address storage circuits or bank data provided from the banks; an output buffer suitable for outputting the output data to a plurality of data input/output pads based on the output clock; and a strobe signal generation circuit suitable for generating a data strobe signal based on the output clock and outputting the data strobe signal through a data strobe pad.