Stacked Memory Dice With Logic Die For Bandwidth
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Solution Overview
Problem
Conventional DRAM devices lack the bandwidth to keep pace with the increasing speeds of processors, leading to performance bottlenecks in computer systems, especially in multi-core processor systems, where they operate at as low as 10% of their potential due to limited data bandwidth.
Innovation Solution
A dual-mode memory system where DRAM die are stacked with a logic die, utilizing a wide bus for high-speed data transfer and implementing packet-based command and address signals to enhance bandwidth, allowing operation in either direct or indirect mode to interface with conventional systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional DRAM devices are used with standard memory interfaces, then compatibility with existing systems is maintained, but data bandwidth is insufficient to keep pace with processor speeds
Solution Approach 1:
The patent transitions from a two-dimensional planar memory architecture to a three-dimensional stacked architecture by placing multiple memory die on top of a single logic die. This vertical stacking enables significantly higher data bandwidth by providing multiple independent memory interfaces that can operate in parallel, allowing the memory system to keep pace with fast processors while maintaining compatibility through dual-mode operation.
Solution Approach 2:
The logic die serves multiple functions: it acts as an interface to conventional systems using standard memory commands and addresses, simultaneously supports high-speed packet-based interfaces for advanced systems, and provides the stacking substrate for multiple memory die. This multi-functionality allows a single memory device to serve both legacy and next-generation systems.
2Productivity
If multiple memory die are stacked on a logic die to increase bandwidth, then data bandwidth is improved, but interface complexity increases requiring packet-based commands
Solution Approach 1:
The memory device dynamically adapts its interface mode based on the connected system. The logic die can operate in conventional mode for systems using standard memory commands or in packet-based mode for systems requiring high-speed packet interfaces. This dynamic adaptability allows the system to optimize for bandwidth when needed while maintaining simplicity when using conventional interfaces.
3Productivity
If wider internal data buses are used to transfer data with higher bandwidth, then data transfer speed is improved, but serialization and deserialization requirements increase interface complexity
Solution Approach 1:
Rather than increasing the width of a single data bus in the horizontal dimension, the patent increases bandwidth by stacking multiple memory die in the vertical dimension. Each die has its own data interface to the logic die, providing parallel data paths without requiring complex serialization of a single wide bus. This approach achieves high bandwidth while keeping individual interface widths manageable.
Data Source
AI summary
Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice.