MRAM Write Circuit Pulse Patterns for Error Rate Reduction

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Solution Overview

Problem

In MRAM technology, the write error rate (WER) is affected by the formation of metastable magnetic domains during the writing process, leading to issues like 'ballooning' and 'back-hopping,' which deviate from theoretical voltage dependencies and cause severe errors, especially in vertical methods where '0'-writing forms metastable domains easily and '1'-writing has weak spin torque, requiring different writing methods for each case.

Innovation Solution

A semiconductor memory device employing a magnetoresistive element with a write circuit that applies distinct pulse patterns for '0'-writing and '1'-writing, using multiple pulses for '0'-writing and a single pulse for '1'-writing, with specific pulse widths and intervals to control magnetization reversal and reduce WER, while maintaining similar total write times for both operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single write pulse is used for both '0'-writing and '1'-writing, then the circuit design is simple, but the write error rate increases due to metastable domain formation in '0'-writing and weak spin torque in '1'-writing

Engineering Contradiction:
Improvewrite error rateVSAvoidwrite pulse pattern complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The write pulse pattern is segmented into two distinct patterns: a first pulse pattern for '0'-writing and a second pulse pattern for '1'-writing. This segmentation allows each pattern to be optimized for its specific writing operation, reducing write error rates caused by metastable domain formation and weak spin torque effects.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The write circuit dynamically selects between different pulse patterns based on the writing operation being performed. The controller determines whether '0'-writing or '1'-writing is required and applies the appropriate pulse pattern, making the system adaptive to different writing conditions.

Inventive Principle:
Principle #15Dynamics

2Reliability

If multiple write pulses are applied to reduce metastable domain formation, then the write error rate decreases, but the write time increases

Engineering Contradiction:
Improvewrite error rateVSAvoidwrite time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The first pulse pattern for '0'-writing employs periodic pulse applications with specific intervals between pulses. This periodic action allows the magnetic domains to stabilize between pulses, reducing metastable domain formation and write error rates while controlling the total write time through optimized pulse timing.

Inventive Principle:
Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces write error rates by optimizing pulse patterns for each writing operation, improving reliability and performance by minimizing metastable state formation and maintaining circuit simplicity.

Implementation Method 1

MRAM writing scheme includes a spin-transfer torque writing method. In the spin-transfer torque writing method, the smaller the size of a magnetic body, the lower a spin-transfer current required for magnetization reversal

Methodology Applied
Scientific EffectSpin-transfer torque:

Implementation Method 2

a magnetoresistive element having a magnetoresistive effect is used in a memory cell storing information

Methodology Applied
Scientific EffectMagnetoresistive effect: Magnetoresistance

Data Source

PatentUS10910032B2Magnetoresistive memory device with different write pulse patterns
Publication Date: 2021.02.02 KIOXIA CORP
  • US10910032B2 patent drawing
  • US10910032B2 patent drawing
  • US10910032B2 patent drawing

AI summary

A memory device includes a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers. The memory device also includes a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a write current to the magnetoresistive element. A first write current in the first writing includes a first pulse and a second pulse added to the first pulse. A width of the second pulse is smaller than a width of the first pulse, and a current level of the second pulse is different from a current level of the first pulse.