Memory Device Dummy Bit Line Charge Sharing

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Solution Overview

Problem

Current memory devices using magnetoresistive effect elements face challenges in high-speed data reading due to unintended switching element turn-on, leading to increased current consumption and reduced operational efficiency.

Innovation Solution

Incorporating a dummy bit line and dummy word line or bit line that can receive read voltage, allowing for charge sharing to control the bit line potential, thereby preventing unintended switching element turn-on and reducing extra current consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional reading operation is performed in memory devices using magnetoresistive effect elements, then data reading can be performed, but unintended switching element turn-on occurs leading to increased current consumption

Engineering Contradiction:
Improvedata reading speedVSAvoidcurrent consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

A dummy bit line is introduced as an intermediary component between the selected bit line and the read circuit. The dummy bit line receives a portion of the read voltage and shares the charge with the selected bit line, thereby mediating the voltage distribution and preventing unintended switching element turn-on while maintaining high-speed data reading capability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dummy bit line is pre-charged to a specific voltage level before the actual reading operation. This preliminary charging action ensures that when the read voltage is applied, the charge sharing between the dummy bit line and selected bit line occurs in a controlled manner, preventing the bit line potential from rising too high and causing unintended switching element activation

Inventive Principle:
Principle #10Preliminary action

2Speed

If read voltage is applied to bit line for high-speed data reading, then reading speed is improved, but bit line potential rises causing unintended switching element turn-on

Engineering Contradiction:
Improvereading speedVSAvoidoperational stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The dummy bit line serves as a voltage buffer and charge reservoir that mediates between the read voltage source and the selected bit line. By distributing the read voltage across both the dummy bit line and selected bit line through charge sharing, the peak potential on the selected bit line is reduced, preventing unintended switching element turn-on while maintaining fast reading speed

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the voltage distribution parameters by introducing a dummy bit line with specific capacitance and pre-charge voltage. This parameter adjustment allows the system to achieve high reading speed with controlled bit line potential, preventing operational instability caused by unintended switching element activation

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables high-speed data reading while minimizing extra current consumption by stabilizing the bit line potential through charge sharing, preventing re-turn-on of the switching element and maintaining efficient operation.

Implementation Method 1

allowing for charge sharing to control the bit line potential

Methodology Applied
Scientific EffectCharge sharing: Capacitance

Implementation Method 2

A memory device using a magnetoresistive effect element is known

Methodology Applied
Scientific EffectMagnetoresistive effect: Magnetoresistance

Data Source

PatentUS20240312506A1Memory device
Publication Date: 2024.09.19 KIOXIA CORP
  • US20240312506A1 patent drawing
  • US20240312506A1 patent drawing
  • US20240312506A1 patent drawing

AI summary

A memory cell includes first and second ends. A first interconnect is coupled to the first end. A first switch is coupled between the first interconnect and a first node that receives a first voltage. A second interconnect is coupled to the second end. A second switch includes a third end coupled to the second interconnect and a fourth end. A third interconnect is coupled to the fourth end. A third switch is coupled between the third interconnect and a second node that receives a second voltage different from the first voltage. A third voltage between the second and first voltages is applied to the first and second interconnects. The third and second switches are respectively turned off and on after the third switch is turned on and after the application of the third voltage. The first switch is turned off after the application of the third voltage.