Semiconductor Memory Device Burst Refresh Control Circuit
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Solution Overview
Problem
As the degree of integration in semiconductor memory devices increases, the coupling effect between word lines leads to row hammering, where data in memory cells adjacent to frequently activated word lines is damaged due to voltage changes and electromagnetic interference, necessitating additional refresh operations to prevent data loss.
Innovation Solution
A semiconductor memory device is designed with a control circuit that generates a latch control signal based on count code signals from first and second clock signals, allowing for efficient target refresh operations during burst refresh cycles, thereby reducing the impact of row hammering by selectively refreshing adjacent word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration is increased to improve memory capacity, then the spacing between word lines is reduced, but the coupling effect between adjacent word lines increases causing row hammering
Solution Approach 1:
The patent applies preliminary action by performing refresh operations on adjacent word lines before data damage occurs due to row hammering. The refresh controller detects frequently activated word lines and proactively refreshes neighboring word lines in advance, preventing data loss before it happens.
Solution Approach 2:
The patent implements feedback through the refresh controller that monitors word line activation frequencies and uses this information to determine which adjacent word lines need refresh operations. The system continuously adjusts refresh targets based on real-time activation patterns, creating a closed-loop protection mechanism against row hammering.
2Reliability
If additional refresh operations are performed to prevent row hammering, then data integrity is improved, but the operational complexity and time consumption increase
Solution Approach 1:
The patent applies local quality by performing refresh operations only on specific adjacent word lines that are identified as needing refresh, rather than refreshing all word lines uniformly. This targeted approach concentrates refresh resources on vulnerable areas while leaving other word lines untouched, reducing overall refresh time and operational overhead.
Solution Approach 2:
The patent uses partial action by performing refresh operations on a subset of word lines (specifically adjacent ones) rather than all word lines in the memory array. This partial refresh strategy provides sufficient protection against row hammering while minimizing the time and energy costs associated with comprehensive refresh operations.
3Speed
If the activation frequency of a word line is increased to improve access speed, then data input/output efficiency is improved, but the coupling effect on adjacent word lines intensifies causing data damage
Solution Approach 1:
The patent converts the harmful voltage changes and coupling effects generated by frequent word line activation into a beneficial monitoring opportunity. By detecting activation frequencies and using them to guide refresh operations, the system transforms the side effects of high-speed access into useful information for proactive data protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves operational reliability by efficiently preventing row hammering during burst refresh modes, ensuring data integrity and reducing the frequency of additional refresh operations.
Implementation Method 1
a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle
Data Source
AI summary
A semiconductor memory device includes a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal; a second count circuit suitable for counting the second clock signal and generating a second count code signal; and a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal.