Strobe Signal Buffer and Division Circuit for Semiconductor Systems

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Solution Overview

Problem

Semiconductor systems face challenges in generating internal strobe signals efficiently for high-speed data input/output operations, as existing methods often result in abnormal strobe signal generation due to phase differences and require significant current consumption.

Innovation Solution

A semiconductor device comprising a strobe signal buffer, a strobe signal division circuit, and a drive control circuit that buffers and divides data strobe signals to generate internal strobe signals with specific phase differences, and drives the buffer output signal to a predetermined logic level during initial write operations, optimizing data capture and reducing current consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If internal strobe signals are generated from external data strobe signals for high-speed data input/output operations, then data transfer speed is improved, but abnormal strobe signal generation occurs due to phase differences

Engineering Contradiction:
Improvedata transfer speedVSAvoidstrobe signal stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

A strobe signal buffer is introduced as an intermediary component between the external data strobe signal input and the internal strobe signal generation. The buffer receives the external data strobe signal and generates a buffered output signal that serves as a stable basis for generating multiple internal strobe signals with controlled phase differences, preventing abnormal signal generation while enabling high-speed operations

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The strobe signal generation process is segmented into distinct functional stages: buffering the external signal, generating the buffered output signal, generating the inverted buffered output signal, and finally generating multiple internal strobe signals with specific phase relationships. This segmentation allows each stage to be optimized independently, ensuring signal stability while achieving high-speed data transfer

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple internal strobe signals with phase differences are generated for high-speed data operations, then productivity is improved, but current consumption increases significantly

Engineering Contradiction:
Improvedata input/output speedVSAvoidcurrent consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The drive control circuit performs preliminary action by controlling the buffer output signal to be driven to a predetermined logic level during an initial section of time from when a write operation is performed. This preliminary control ensures that the strobe signal buffer and division circuit operate with optimized timing, generating internal strobe signals only when necessary for high-speed data operations, thereby reducing unnecessary current consumption while maintaining productivity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts the operation of the strobe signal buffer and division circuit based on the write operation timing. The drive control circuit modulates the buffer output signal driving during the initial section of time, enabling the internal strobe signals to be generated with dynamic timing control. This dynamic operation allows high-speed data input/output when needed while reducing current consumption during non-critical periods

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10026461B2Semiconductor devices and semiconductor systems including the same
Publication Date: 2018.07.17 SK HYNIX INC
  • US10026461B2 patent drawing
  • US10026461B2 patent drawing
  • US10026461B2 patent drawing

AI summary

A semiconductor device may include a strobe signal buffer, a strobe signal division circuit, and a drive control circuit. The strobe signal buffer may buffer a first data strobe signal and a second data strobe signal to generate a buffer output signal and an inverted buffer output signal. The strobe signal division circuit may divide the buffer output signal and the inverted buffer output signal to generate internal strobe signals which are used in capturing data when receiving data. The drive control circuit may drive the buffer output signal to a predetermined logic level during an initial section of time from a point of time when a write operation is performed.