Self-Timed Pulse Input Latch for Fast Memory Access
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Solution Overview
Problem
Existing memory circuits face challenges in achieving fast address access for read and write operations in the same cycle due to setup and hold time constraints, which limit their efficiency and speed.
Innovation Solution
The implementation of a self-timed pulse input latch circuitry scheme that allows for asynchronous operation by utilizing a self-timed pulse generator to create a positive or negative pulse at the rising edge of the clock, enabling read and write operations to be performed independently of cycle time and clock edges, with the input latch being in a transparent state before the next clock rising edge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous operation with input register is used, then proper clock registration is achieved, but setup and hold time constraints limit access speed
Solution Approach 1:
The patent segments the address input into two independent registers: a first input register for row address and a second input register for column address. This segmentation allows each register to be independently controlled and registered at different clock edges, eliminating the bottleneck of sequential address registration while maintaining proper synchronous operation. The row and column addresses can be registered simultaneously or in different phases, significantly improving access speed without sacrificing reliability.
Solution Approach 2:
The patent implements preliminary registration of addresses in the input registers before the actual memory access operation. By pre-registering the row and column addresses in separate input registers during the setup phase, the memory array can be accessed immediately when both addresses are ready, eliminating the need to wait for sequential registration and improving overall access speed while ensuring proper clock synchronization.
2Productivity
If fast address access is implemented, then read and write operations can occur in the same cycle, but setup and hold time requirements are violated
Solution Approach 1:
The patent employs dynamic control of the input registers using different clock edges (rising and falling edges). The first input register can be registered on the rising edge while the second input register is registered on the falling edge, or vice versa. This dynamic approach allows flexible timing control that accommodates fast read and write operations in the same cycle while still meeting setup and hold time requirements through proper clock phase management.
Solution Approach 2:
The patent utilizes periodic clock cycles with distinct rising and falling edges to control the registration of row and column addresses. By assigning different addresses to different phases of the periodic clock cycle, the system can accept new addresses during one phase while completing access operations in another phase, enabling high throughput while maintaining precise timing control through the regular clock waveform.
3Reliability
If traditional input register scheme is used, then synchronous operation is maintained, but random access time increases
Solution Approach 1:
By segmenting the address input into separate registers for row and column addresses, the patent enables parallel or independent registration of each address component. This segmentation eliminates the sequential registration delay inherent in traditional single-register schemes, reducing random access time while maintaining synchronous operation through independent clock edge control for each segmented register.
Data Source
AI summary
Systems and methods relating to memory and/or memory latching are disclosed. In one exemplary implementation, an illustrative memory device may include self-timed pulse generator circuitry, first input latch circuitry, read/write control circuitry, and second input latch circuitry. According to further implementations herein, fast address access for read and write may be provided in the same cycle via a self-timed pulse in the input latch circuit and/or via associated control/scheme from the control circuit.