DRAM Refresh Controller Skipping Unaccessed Rows
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-performance memory devices, such as DRAM, require frequent refresh operations, leading to increased power consumption and reduced efficiency due to the need for periodic refreshing of memory cells as integration levels rise.
Innovation Solution
A memory device with a refresh controller and access information storage circuit that uses flag information to skip refresh operations for accessed rows, reducing unnecessary refreshes and optimizing power usage by storing flag information in registers to determine whether a refresh operation is required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed periodically for all rows in high-performance memory devices, then data retention is maintained, but power consumption increases and efficiency decreases
Solution Approach 1:
The patent applies local quality by differentiating refresh operations based on individual row characteristics. Instead of uniformly refreshing all rows, the system identifies and refreshes only those rows that require it (unaccessed rows), while skipping rows that have been recently accessed and still retain data. This selective approach reduces overall power consumption while maintaining data retention for rows that need it.
Solution Approach 2:
The patent implements self-service through the refresh controller that automatically monitors row access status via flag information and autonomously decides which rows need refreshing. The system uses the inherent access information already available in the memory device to make refresh decisions, eliminating the need for external control and reducing unnecessary refresh operations.
2Reliability
If refresh operations are performed frequently to maintain data integrity, then reliability is improved, but the interval between refresh commands decreases reducing operational efficiency
Solution Approach 1:
The patent extracts the unnecessary refresh operations from the periodic refresh schedule by identifying rows that do not require refreshing (accessed rows with valid flag information). By removing these redundant operations, the system maintains data integrity for rows that need it while increasing the interval between refresh commands, thereby improving operational efficiency and productivity.
Solution Approach 2:
The patent applies dynamics by making the refresh interval variable rather than fixed. The refresh controller dynamically adjusts the timing and frequency of refresh operations based on real-time row access patterns and flag information. This dynamic approach allows longer intervals between refresh commands when few rows need refreshing, while maintaining data integrity when necessary.
3Quantity of substance
If the degree of integration of DRAM is increased, then memory capacity is improved, but the number of refresh operations increases leading to higher power consumption
Solution Approach 1:
The patent applies local quality by implementing row-specific refresh control in high-capacity DRAM devices. Each row has associated flag information that tracks its access status, allowing the refresh controller to selectively refresh only the necessary rows. This approach scales efficiently with increased memory capacity, as the selective refresh mechanism reduces the proportion of rows requiring refresh operations, thereby mitigating the power consumption increase that would otherwise result from higher integration levels.
4Use of energy by moving object
If refresh operations are controlled based on row access characteristics, then power consumption is reduced, but device complexity increases due to additional control circuits
Solution Approach 1:
The patent applies universality by designing the refresh controller to perform multiple functions: it monitors row access status, manages flag information, determines refresh requirements, and executes refresh operations. The access information storage circuit also serves dual purposes by tracking both access patterns and refresh status. This multi-functional design reduces the need for separate dedicated circuits, thereby limiting the increase in device complexity while achieving power reduction through selective refreshing.
Data Source
AI summary
Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row.