Shared Operational Amplifier for Semiconductor Storage Read and Write
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Solution Overview
Problem
Conventional PCM and iPCM devices waste current after data writing due to separate write and read circuits, leading to reliability degradation from excessive write operations.
Innovation Solution
A semiconductor storage device with a shared operational amplifier for both read and write operations, allowing for parallel data detection and immediate cessation of write current, reducing circuit scale and current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If separate write circuit and read circuit are provided, then data write and read operations can be performed independently, but current is wasted after data writing is completed and reliability is degraded
Solution Approach 1:
The patent combines the write circuit and read circuit into a single integrated circuit that can perform both write and read operations. The circuit includes a write transistor for writing data and a read transistor for reading data, both controlled by a shared control signal. This merging allows the circuit to switch between write and read modes without requiring separate dedicated circuits, thereby eliminating wasteful current flow after write operations while maintaining independent operation capability.
Solution Approach 2:
The patent implements dynamic control of the circuit functionality through a control signal that switches the circuit between write mode and read mode. The write transistor and read transistor are dynamically activated based on the operation type, allowing the circuit to adapt its behavior to the current task. This dynamic switching prevents excessive write operations by immediately stopping write current flow when the write operation is complete, thus improving reliability.
2Adaptability or versatility
If separate write circuit and read circuit are provided, then write and read functions are independent, but circuit scale increases and current consumption increases
Solution Approach 1:
The patent designs a universal circuit that can perform both write and read operations using shared components. The same bit line, sense node, and control mechanisms are used for both write and read functions. The circuit includes a write transistor for data writing and a read transistor for data reading, both integrated into the same circuit structure. This multi-functional design reduces circuit scale by eliminating redundant components while maintaining the versatility to perform independent write and read operations.
3Ease of operation
If separate write circuit and read circuit are provided, then write and read operations can be performed separately, but current consumption increases due to wasteful current flow
Solution Approach 1:
The patent implements a feedback mechanism where the completion of a write operation is detected and used to control the write current flow. When data writing is complete, the control circuit receives feedback and immediately stops the write current flow by deactivating the write transistor. This feedback-based control eliminates wasteful current consumption after write operations while maintaining the ability to perform separate write and read operations efficiently.
Solution Approach 2:
The patent uses periodic control signals to alternately activate write and read operations. The control circuit applies write voltage during write operations and read voltage during read operations in a periodic manner, ensuring that write current flows only when necessary and not continuously. This periodic action pattern reduces current consumption by eliminating idle current flow between operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances reliability by minimizing wasteful current consumption and preventing excessive write operations, while maintaining efficient data storage and retrieval processes.
Implementation Method 1
the PCM and the iPCM are brought to a low-resistance state (a set state) or a high-resistance state (a reset state) due to phase transition of a phase-change film of a memory cell
Data Source
AI summary
A semiconductor storage device according to the present embodiments includes a first bit line and a first word line. A resistance-change memory element is connected to the first bit line and the first word line. A sense node is connected to the first bit line in a data read operation. A first transistor is connected between the sense node and the first bit line. A second transistor connects the first bit line and a power supply to each other in a data write operation. A first operational amplifier has one input connected to the first bit line, other input receiving a reference voltage, and an output connected in common to a gate of the first transistor and a gate of the second transistor. A sense circuit is connected to the sense node.