Internal Voltage Generation Circuit for Rapid Mode Transition
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Solution Overview
Problem
Conventional peri-voltage generation circuits in semiconductor memories take a long time to raise the peri-voltage from standby to active mode and experience power dissipation due to leakage current during mode transitions.
Innovation Solution
The proposed internal voltage generation circuit includes a first enable signal generator to delay the active signal, a comparison signal generator, a pulse signal generator, and a drive device to rapidly adjust the peri-voltage from 1.2V to 1.8V using NMOS and PMOS transistors, minimizing leakage current and power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the standby internal voltage generator is shut off during mode transition, then power dissipation is reduced, but the active internal voltage generator takes much time to raise the peri-voltage to the target level
Solution Approach 1:
The patent applies preliminary action by keeping the standby internal voltage generator in a partially active state during mode transitions. Instead of completely shutting it off, the generator maintains readiness to quickly supply voltage, thereby reducing the transition time while still managing power dissipation through controlled operation rather than full shutdown and restart cycles.
2Loss of time
If the standby internal voltage generator remains active during mode transition, then voltage transition time is reduced, but leakage current flows causing power dissipation
Solution Approach 1:
The patent applies dynamics by dynamically adjusting the operational state of the standby internal voltage generator based on the current mode transition requirements. The generator transitions between different operational states (fully active, partially active, standby) depending on whether a mode change is detected, allowing optimal balance between response time and power consumption rather than maintaining a fixed state.
Solution Approach 2:
The patent uses feedback mechanisms to monitor the operational mode of the semiconductor memory device and automatically control the state of the standby internal voltage generator. When a mode transition is detected, the system feedback controls the generator to remain in a low-power state; when no transition is detected, the generator can remain active to provide quick voltage supply, thus optimizing both power dissipation and response time based on real-time system state.
3Productivity
If the peri-voltage is rapidly raised from 1.2V to 1.8V during mode transition, then productivity is improved, but device complexity increases due to additional control circuits
Solution Approach 1:
The patent applies universality by designing the internal voltage generation circuit to perform multiple functions through a single integrated control mechanism. The same control logic that manages the standby generator's operational state also handles the mode transition detection and coordination, eliminating the need for separate dedicated control circuits for each function and thereby reducing overall device complexity while maintaining rapid transition capability.
Data Source
AI summary
An internal voltage generation circuit includes a first enable signal generator configured to delay an active signal to generate a first enable signal, a comparison signal generator configured to compare the internal voltage with an internal reference voltage to generate a comparison signal, a pulse signal generator configured to receive the first enable signal and to generate a pulse signal, a transmission device configured to buffer and transfer the comparison signal as a pull-down signal, and a drive device configured to drive the driving signal to the first level in response to the pull-down signal.