Dynamic Wear Leveling for Non-Volatile Memory Block Endurance
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Solution Overview
Problem
Conventional wear leveling algorithms in non-volatile memory devices assume consistent lifetime for all memory blocks, leading to underestimation or overestimation of endurance, resulting in inefficient utilization and risk of data loss, and require additional space for cycle count management.
Innovation Solution
A memory device with a sensing unit and controller that senses characteristic deviations of individual memory cells, using testing pulses to assess their health and adjust programming accordingly, allowing for flexible management and avoiding risky blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conservative wear leveling algorithm with a low specific threshold of programming cycle count is used, then data reliability is improved, but memory block utilization deteriorates due to underestimation of endurance
Solution Approach 1:
The patent changes the parameter of threshold determination from a fixed conservative value to a dynamic value based on actual memory block characteristics. By monitoring programming cycle counts and comparing them against block-specific thresholds rather than a universal conservative threshold, the system adapts to the actual endurance of each memory block, thereby improving utilization without sacrificing reliability
Solution Approach 2:
The patent implements feedback mechanisms by continuously monitoring the programming cycle counts of memory blocks and using this information to adjust wear leveling decisions. The controller receives feedback on actual block usage and endurance characteristics, then dynamically adjusts the specific threshold for each block, allowing the system to optimize utilization based on real-time conditions while maintaining data reliability
2Productivity
If an aggressive wear leveling algorithm with a high specific threshold of programming cycle count is used, then memory block utilization is improved, but data reliability deteriorates due to overestimation of endurance
Solution Approach 1:
The patent changes the threshold parameter from a fixed aggressive value to a dynamic, block-specific value determined through monitoring and comparison. By adjusting the specific threshold for each memory block based on its actual programming cycle count and endurance characteristics, the system avoids the blanket overestimation problem of aggressive algorithms while still achieving high utilization
Solution Approach 2:
The patent uses feedback on actual memory block performance to adjust wear leveling parameters. By continuously monitoring programming cycle counts and using this feedback to determine appropriate specific thresholds for each block, the system prevents overestimation of endurance while maintaining high utilization rates
3Device complexity
If conventional wear leveling algorithms assume consistent lifetime for all memory blocks, then device complexity is reduced, but measurement precision deteriorates due to inability to detect actual block health variations
Solution Approach 1:
The patent applies local quality by treating each memory block individually with its own specific threshold and monitoring parameters, rather than applying a uniform assumption to all blocks. This localized approach to health assessment improves measurement precision by capturing actual variations in block characteristics while maintaining manageable complexity through systematic implementation
4Measurement precision
If additional space is allocated for cycle count management in conventional wear leveling, then measurement precision is improved, but device complexity increases due to overhead requirements
Solution Approach 1:
The patent merges the wear leveling management functions by consolidating threshold determination and cycle count monitoring into an integrated controller process. This merging eliminates the need for separate overhead structures for cycle count management, achieving precise measurement while reducing device complexity through functional integration
Data Source
AI summary
A memory device and associated controlling method are provided. The memory device includes a memory cell array, a sensing unit and a controller. The memory cell array has a plurality of memory cells. The sensing unit is electrically connected to the memory cell array and the controller. The sensing unit senses characteristic of a memory cell of the plurality of memory cells. The controller determines whether the characteristic of the one of the memory cells deviates and accordingly controls the memory cell array.