RTA Memory Control Logic for Switch Area Reduction
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Solution Overview
Problem
Current SRAM designs operating in retention till access (RTA) mode face challenges with high switch area and peak current requirements, leading to increased system-on-chip (SoC) area and leakage, due to the need for large decoupling capacitance, which is difficult to predict and results in conservative capacitance values.
Innovation Solution
The proposed solution involves an SRAM configuration with an input latch, address flop, and RTA generation logic that generates an RTA enable signal one clock cycle before memory block access, allowing the array supply voltage to charge earlier, reducing the size of the RTA switch and peak current, and improving memory performance by charging the supply voltage outside the memory read/write path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the size of the RTA switch is increased to support high memory performance, then the peak current capability is improved, but the switch area and decoupling capacitance requirements increase
Solution Approach 1:
The patent applies preliminary action by generating the RTA enable signal one clock cycle before the memory block access. This early activation allows the array supply voltage to begin charging in advance, so that when the actual access occurs, the voltage is already at the required level. This eliminates the need for large decoupling capacitance and reduces the RTA switch size, as the charging process is spread over time rather than requiring instantaneous current delivery.
2Productivity
If large decoupling capacitance is used to support high peak current, then the memory performance is improved, but the overall SoC area and leakage increase
Solution Approach 1:
The patent eliminates the need for large decoupling capacitance by performing preliminary charging of the array supply voltage one clock cycle before access. The RTA generation logic produces an enable signal in advance, allowing the supply voltage to ramp up gradually through the RTA switch. This time-distributed charging approach replaces the need for large instantaneous current capability, thereby removing the requirement for large decoupling capacitance and reducing SoC area.
3Reliability
If conservative value of decoupling capacitance is used to account for unpredictable peak current, then the reliability is improved, but the SoC area and leakage increase
Solution Approach 1:
The patent improves reliability without requiring conservative over-provisioning of decoupling capacitance by using preliminary action. The RTA enable signal is generated one clock cycle before access based on predicted address patterns from the address flop and pre-decoder. This allows the system to reliably support the actual peak current requirements without adding excess capacitance, thereby reducing leakage while maintaining reliability.
Solution Approach 2:
The patent employs feedback by using the address flop and pre-decoder to predict which memory block will be accessed next. This prediction feedback allows the RTA generation logic to proactively activate the appropriate RTA switch one clock cycle in advance, ensuring that the array supply voltage is charged to the correct level before the actual access occurs. This feedback mechanism eliminates the need for conservative capacitance sizing.
Data Source
AI summary
A memory configurable to be used in an RTA mode includes an input latch configured to receive an input address bus and to generate a latched address bus that corresponds to a memory location. An address flop is configured to save the latched address and to generate a flopped address. A first block address pre-decoder stage is configured to generate a pre-decoded latched address to an RTA generation logic in response to the latched address bus; and a second block address pre-decoder configured to generate a pre-decoded flopped address to the RTA generation logic in response to the flopped address. The RTA generation logic generates an RTA enable signal one clock cycle before a memory block access, to activate a memory block corresponding to the memory location, such that an array supply voltage of the memory block starts charging one clock cycle before a memory block access.