Word Line Driver Level Shifting for Memory
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Solution Overview
Problem
Conventional level shifting implementations in multiple-voltage-domain memories require large substrate areas and slow circuitry, hindering their use in memory topologies with small memory cell pitches and impeding performance due to their placement in the critical path between peripheral circuitry and word lines.
Innovation Solution
A word line driver with transistors using a thicker gate oxide for the bit cell array and peripheral circuitry, allowing for efficient voltage level shifting between different voltage domains, enabling faster operation and reduced leakage current while maintaining data retention during low-power modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional level shifting implementations are used, then voltage level shifting between domains is achieved, but substrate area becomes large and circuit speed becomes slow
Solution Approach 1:
The patent combines the voltage level shifting function with the existing word line driver circuitry by integrating level shifting transistors directly into the word line driver structure. This merging eliminates the need for separate conventional level shifting circuits, thereby reducing substrate area while maintaining voltage domain isolation capability.
Solution Approach 2:
The word line driver circuit is designed to perform multiple functions: driving word lines in the high-voltage domain and simultaneously performing voltage level shifting from the low-voltage peripheral domain. This multi-functionality eliminates the need for dedicated level shifting circuits, reducing overall circuit area.
2Adaptability or versatility
If conventional level shifting implementations are used, then voltage level shifting between domains is achieved, but circuit operation speed becomes slow
Solution Approach 1:
By merging the level shifting function into the word line driver, the patent eliminates additional circuit stages that would introduce delays. The level shifting transistors are positioned to directly control word line activation, reducing the critical path length and improving signal propagation speed.
Solution Approach 2:
The level shifting transistors are pre-configured in the word line driver circuit to immediately respond when peripheral control signals are activated. This preliminary arrangement of control transistors enables faster voltage domain transition without requiring sequential switching operations.
3Reliability
If word line drivers operate at higher voltage, then data retention and performance are improved, but leakage current in peripheral circuitry increases
Solution Approach 1:
The patent segments the memory system into two distinct voltage domains: a high-voltage domain for the bit cell array and word line drivers (for optimal data retention and performance) and a low-voltage domain for peripheral circuitry (for reduced leakage current). Independent voltage control for each domain resolves the contradiction between retention and energy loss.
Solution Approach 2:
The level shifting circuit acts as an intermediary between the low-voltage peripheral domain and the high-voltage word line driver domain. It enables the peripheral circuitry to control high-voltage word lines without requiring the peripheral circuitry itself to operate at high voltage, thus maintaining low leakage current while achieving reliable data retention.
Data Source
AI summary
A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.