Memory Controller Latency Signal Stability for pSRAM
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Solution Overview
Problem
Conventional memory controllers for pseudo static random access memory (pSRAM) experience malfunctions due to short time intervals for chip select signal transitions, leading to incorrect switching of latency control signals, which affects the read/write data strobe signal and prevents valid data writing under correct timing sequences.
Innovation Solution
A memory controller with a mode register, mode register write controller, and latency controller that maintains the latency type control signal at a high voltage level using a write mask signal when the inverted chip select signal is disabled, preventing malfunctions in the read/write data strobe signal during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the chip select signal transitions quickly to enable latency control signal switching, then the response speed is improved, but the latency control signal cannot switch in time during short time intervals causing malfunction
Solution Approach 1:
The write mask signal is generated in advance based on the chip select signal state before the latency control signal needs to switch. By preliminarily determining the write operation state and preparing the appropriate latency control signal level, the system ensures reliable signal switching even during short time intervals when the chip select signal transitions quickly.
Solution Approach 2:
The write mask signal acts as an intermediary between the chip select signal and the latency control signal. It mediates the control relationship by determining the latency control signal level based on the chip select signal state, ensuring that the latency control signal switches correctly without being directly affected by the rapid transitions of the chip select signal.
2Speed
If the latency control signal switches rapidly to adjust access latency, then the access latency adjustment speed is improved, but the read/write data strobe signal malfunctions due to insufficient switching time
Solution Approach 1:
The system preliminarily determines the required latency control signal level by detecting the chip select signal state and generating the write mask signal in advance. This preliminary action ensures that when the latency control signal needs to switch, it can do so reliably without causing read/write data strobe signal malfunction, even during rapid access latency adjustments.
Solution Approach 2:
The write mask signal serves as an intermediary that ensures the latency control signal switches correctly during rapid access latency adjustments. By mediating the control relationship, it prevents the read/write data strobe signal from malfunctioning while still enabling fast access latency adjustment.
3Loss of time
If the time interval for chip select signal transition is shortened to improve response time, then the response time is improved, but the latency control signal cannot switch in time causing write operation malfunction
Solution Approach 1:
The write mask signal is generated in advance based on the chip select signal state, before the latency control signal needs to switch. This preliminary action allows the system to maintain reliable write operations even when the chip select signal transitions occur within short time intervals, as the latency control signal level is already determined.
Solution Approach 2:
The write mask signal acts as an intermediary that decouples the timing relationship between the chip select signal and the latency control signal. It ensures that the latency control signal can switch reliably even when the chip select signal transitions occur rapidly, preventing write operation malfunction.
Data Source
AI summary
A memory controller is provided. The memory controller is suitable for a pseudo static random access memory. The memory controller includes a mode register, a mode register write controller and a latency controller. The mode register is configured to generate a latency control signal according to a write instruction signal. The mode register write controller is configured to generate the write instruction signal during a mode register write operation and generate a write mask signal according to a chip selection signal. The latency controller generates a latency type control signal according to the latency control signal and the write mask signal.