Semiconductor Bit Line Equalizing Circuit Timing Control
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Solution Overview
Problem
In semiconductor devices, the low internal voltage for reducing power consumption leads to longer equalizing operations due to small gate-source and gate-drain voltages in equalizing circuits, and using external potential as an equalizing signal complicates timing adjustments with word lines, potentially causing erroneous equalizing operations.
Innovation Solution
A semiconductor device with a timing control circuit generating an equalizing signal and a timing signal with adjustable amplitude, an equalizing control circuit converting the signal to a higher potential, and a word driver that adjusts sub-word line timings based on this potential, allowing the use of external potential without a booster circuit and ensuring synchronized equalizing and word line reset operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If internal voltage is lowered to reduce power consumption, then power consumption is reduced, but equalizing operation time increases due to small gate-source and gate-drain voltages
Solution Approach 1:
The equalizing operation is segmented into two stages: first, a preliminary equalizing operation using a preliminary equalizing signal; second, a main equalizing operation using a main equalizing signal. This segmentation allows the system to perform equalization in phases, reducing the total time required while operating at low internal voltage.
Solution Approach 2:
The preliminary equalizing signal is generated before the main equalizing signal to pre-charge the bit lines to an intermediate potential. This preliminary action reduces the voltage difference that needs to be bridged during the main equalizing operation, thereby reducing the overall equalizing time even at low internal voltages.
2Device complexity
If external potential VDD is used as equalizing signal, then circuit scale and power consumption are suppressed, but timing adjustment becomes difficult and erroneous equalizing operations may occur
Solution Approach 1:
An equalizing control circuit is introduced as an intermediary between the external potential VDD and the equalizing circuit. This intermediary circuit generates the equalizing signal by converting the external potential through controlled transistor switching, thereby maintaining timing accuracy while using the external potential to reduce circuit scale.
Solution Approach 2:
The equalizing control circuit incorporates feedback mechanisms to monitor and adjust the equalizing signal timing based on the internal potential conditions. This feedback ensures that the equalizing operation starts at the correct timing regardless of external potential variations, preventing erroneous equalizing operations.
3Power
If boost potential is used as equalizing signal, then sufficient ON-current is achieved, but circuit scale and power consumption increase
Solution Approach 1:
The equalizing signal generation is segmented into two parts: a preliminary equalizing signal that does not require boost potential, and a main equalizing signal that uses the external potential VDD. This segmentation achieves sufficient ON-current for the main operation without requiring a boost potential circuit throughout the entire equalizing process.
Solution Approach 2:
The preliminary equalizing signal pre-charges the bit lines to an intermediate potential before the main equalizing operation. This preliminary action reduces the voltage difference that needs to be bridged during the main operation, allowing the use of external potential VDD without requiring a boost potential circuit.
Data Source
AI summary
A semiconductor device includes: a sense amplifier including an equalizing circuit that equalizes a pair of bit lines; an equalizing control circuit that converts the amplitude of an equalizing signal into a VDD level, and a word driver that controls a sub word line based on a timing signal. The word driver includes a level shift circuit for changing the operation timing of the sub word line in accordance with the VDD level, allowing a timing to complete the equalizing operation and a timing to reset the sub word line to synchronize even when the level of the VDD level is changed.