SRAM Read Assist Circuit with PVT Tracking
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Solution Overview
Problem
Existing read assist circuits for SRAM memory cells fail to effectively track supply voltage variations, leading to performance and power penalties due to inadequate wordline underdrive voltage adjustment across process, voltage, and temperature (PVT) conditions, resulting in slowed read operations and potential write failures.
Innovation Solution
A read assist circuit with a bias circuit that applies a PVT-dependent biasing voltage to a pull-down transistor to modulate wordline underdrive voltage, incorporating voltage tracking, process tracking, and temperature tracking mechanisms to adjust the control signal for optimal performance across varying conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed wordline underdrive voltage is used in read assist circuits, then the circuit structure is simple, but the static noise margin becomes insufficient under varying process, voltage, and temperature conditions, leading to performance degradation and write failures
Solution Approach 1:
The patent implements dynamic adjustment of the wordline underdrive voltage through a bias circuit that responds to PVT conditions. The bias circuit dynamically modifies the control signal voltage based on detected process, voltage, and temperature variations, allowing the read assist circuit to adapt its wordline underdrive strength in real-time to maintain sufficient static noise margin across varying operating conditions.
Solution Approach 2:
The patent changes the voltage parameter of the control signal applied to the pull-down transistor based on PVT conditions. By adjusting the control signal voltage level dynamically, the bias circuit modifies the effective wordline underdrive voltage to compensate for PVT variations, thereby maintaining reliable read and write operations without requiring complete redesign of the memory cell structure.
2Reliability
If the wordline underdrive voltage is increased to maintain static noise margin, then reliability improves, but power consumption increases and read operation speed decreases
Solution Approach 1:
The bias circuit dynamically adjusts the wordline underdrive voltage based on actual PVT conditions rather than using a fixed high voltage. This dynamic adjustment allows the system to apply the minimum necessary underdrive strength to maintain static noise margin, avoiding the continuous power consumption and speed penalty that would result from always using a high fixed underdrive voltage. The read operation speed is preserved by only applying increased underdrive when actually needed for reliability.
3Adaptability or versatility
If voltage tracking is added to the read assist circuit to compensate for supply voltage variations, then performance across PVT conditions improves, but the circuit complexity and power consumption increase
Solution Approach 1:
The bias circuit implements voltage tracking through a feedback mechanism that detects supply voltage variations and adjusts the control signal voltage accordingly. This feedback-based approach allows the circuit to automatically compensate for voltage droop or variations without requiring complex external control logic or continuous high-power operation, thereby achieving improved adaptability with moderate power overhead.
Data Source
AI summary
A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node. A bias circuit applies a biasing voltage to the gate terminal of the n-channel pull-down transistor that is modulated responsive to process, voltage and temperature conditions in order to provide controlled word line underdrive.