Dual-Inverter Memory Device Control Transistor Leakage Prevention
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Solution Overview
Problem
Electric current leakage during write operations in memory devices adversely affects their performance.
Innovation Solution
A memory device configuration including a control transistor connected to both the output terminal of a first inverter and the input terminal of a second inverter, which is configured to be off during write operations, and a method that disconnects the output terminal of the first inverter from the input terminal of the second inverter during write operations, minimizing electrical connections and preventing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the output terminal of the first inverter is continuously connected to the input terminal of the second inverter, then the memory device can maintain normal read and hold operations, but electric current leakage occurs during write operations affecting performance
Solution Approach 1:
The patent applies the dynamics principle by making the control transistor's on/off state changeable based on operation mode. The control transistor is configured to be off during write operations to disconnect the inverters and prevent current leakage, while being on during read and hold operations to maintain normal functionality. This dynamic state change allows the system to adapt its electrical connection state according to operational requirements, resolving the contradiction between continuous connection benefits and write operation performance.
2Object-generated harmful factors
If the control transistor is turned off during write operations to prevent current leakage, then electric current leakage is minimized, but the electrical connection between inverters is disconnected
Solution Approach 1:
The patent applies the extraction principle by isolating the control transistor from the main inverter circuit during write operations. By turning off the control transistor, the electrical connection between the first and second inverters is extracted or removed, preventing current leakage paths. This selective disconnection allows the system to eliminate harmful current flow without permanently altering the fundamental circuit architecture, thus managing device complexity effectively.
3Ease of operation
If the control transistor is configured to be on during read and hold operations, then normal memory operations are maintained, but current leakage may occur during write operations
Solution Approach 1:
The patent applies dynamics by configuring the control transistor with different on/off states corresponding to different operation modes. During read and hold operations, the control transistor is on to maintain normal electrical connections and ease of operation. During write operations, it switches to off state to prevent current leakage. This dynamic reconfiguration allows the system to optimize for different operational requirements without compromise.
Data Source
AI summary
A memory device may include a first inverter, a second inverter, and a control transistor. The control transistor is electrically connected to each of an output terminal of the first inverter and an input terminal of the second inverter for controlling an electrical connection between the output terminal of the first inverter and the input terminal of the second inverter.