Memory Section Control Circuit GIDL Leakage Reduction
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Solution Overview
Problem
Contemporary memory devices face significant power consumption issues due to gate-induced diode leakage (GIDL) currents, particularly during self-refresh operations, as numerous word line drivers are activated simultaneously, leading to substantial unwanted power consumption even in inactive sections.
Innovation Solution
The solution involves regulating the word line driver voltage by maintaining the VCC voltage for inactive memory sections and only switching to VCCP voltage when necessary, thereby reducing the frequency of charging and discharging between VCC and VCCP, and ensuring that inactive memory sections operate with reduced voltage to minimize GIDL currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If VCCP voltage is provided to the gate of the nFET to quickly deactivate the word line, then the word line deactivation speed is improved, but gate-induced diode leakage current increases causing substantial unwanted power consumption
Solution Approach 1:
The patent applies dynamics by making the word line driver voltage selectable and time-varying. The memory section control circuit dynamically switches between VCC and VCCP voltages based on operational needs: VCCP is used during self-refresh operations for fast deactivation, while VCC is used during normal operations to minimize leakage. This dynamic voltage selection resolves the contradiction between fast deactivation speed and low power consumption.
Solution Approach 2:
The patent changes the voltage parameter of the word line driver based on operational mode. By providing different voltage levels (VCC vs VCCP) to the word line driver, the system optimizes performance for different scenarios: lower voltage VCC reduces GIDL current during normal operations, while higher voltage VCCP enables fast word line deactivation during self-refresh operations when needed.
2Reliability
If VCCP voltage is continuously provided to memory sections during self-refresh operations, then word line deactivation performance is improved, but power consumption increases due to frequent charging and discharging
Solution Approach 1:
The patent applies local quality by providing different voltage levels to different memory sections based on their operational state. Active memory sections receiving VCCP voltage maintain reliable word line driver performance, while inactive memory sections receive VCC voltage to minimize power consumption. This localized voltage assignment allows the system to maintain performance where needed while reducing overall power consumption during self-refresh operations.
3Productivity
If the voltage on the Vccprdec node is frequently charged and discharged between VCC and VCCP during row refresh operations, then word line activation and deactivation is achieved, but unwanted current consumption increases
Solution Approach 1:
The patent applies periodic action by implementing a self-refresh operation mode where memory sections are refreshed periodically rather than continuously. During self-refresh, the Vccprdec node voltage is updated only when necessary (periodically) rather than with every row access. This periodic updating reduces the frequency of charging and discharging cycles, thereby reducing unwanted current consumption while maintaining the necessary row refresh capability.
Data Source
AI summary
Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.