Semiconductor Bank Group Addressing for Column Operation
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Solution Overview
Problem
Current semiconductor devices face challenges in efficiently performing column operations across multiple bank groups due to limitations in command pulse generation and address management, leading to increased operation time and power consumption.
Innovation Solution
The semiconductor device incorporates a read/write control circuit, column control pulse generation circuit, and bank group address generation circuit to generate and manage command pulses and addresses for performing column operations across selected bank groups, allowing for efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single bank group is selected for column operations, then the address management is simplified, but the operation time increases due to sequential processing
Solution Approach 1:
The patent divides the bank address into two independent segments: a first bank group selection signal (2 bits) that selects one of four bank groups, and a second bank address signal (2 bits) that selects one of four banks within the selected bank group. This segmentation allows parallel column operations across multiple bank groups while keeping address management organized and manageable through separate signal paths.
2Speed
If multiple bank groups are operated simultaneously, then the operation speed increases, but the command pulse generation becomes more complex
Solution Approach 1:
The patent generates all four column control pulses (first through fourth) and all four internal column control pulses (first through fourth) in advance, before they are needed for actual column operations. These pre-generated pulses are stored and then activated based on the bank group selection, enabling simultaneous multi-bank group operations without complex real-time pulse generation logic.
3Productivity
If separate command pulses are generated for each bank group, then the simultaneous operation capability is improved, but the power consumption increases
Solution Approach 1:
The patent employs periodic column control pulses with different timing characteristics: the first and second column control pulses are generated at different time points, as are the third and fourth pulses. This periodic structure allows the circuit to enable simultaneous operations across bank groups while controlling power consumption by activating pulses in a structured, time-separated manner rather than continuously.
Data Source
AI summary
A semiconductor device includes a read write control circuit, a bank group selection signal generation circuit, and a bank group address generation circuit. The read write control circuit generates a read bank group selection signal from an external control signal to perform a read operation and generates a write command pulse from the external control signal to perform a write operation. The bank group selection signal generation circuit stores a bank address based on the write command pulse and outputs the stored bank address as a bank group selection signal at a time different from a time that the bank address is stored. The bank group address generation circuit generates a bank group address and an internal bank group address for performing a column operation of a cell array included in a bank group selected based on the read bank group selection signal and the bank group selection signal.